Renesas RX100 Series User Manual page 108

RX13T Group
When erasing the block including the OFS0 register, the OFS0 register value becomes FFFF FFFFh.
The setting in the OFS0 register is ignored in boot mode, and this register functions similarly when it is set to FFFF
FFFFh.
IWDTSTRT Bit (IWDT Start Mode Select)
This bit selects the mode in which the IWDT is activated after a reset (stopped state or activated in auto-start mode).
When activated in auto-start mode, the OFS0 register setting for the IWDT is effective.
IWDTTOPS[1:0] Bits (IWDT Timeout Period Select)
These bits select the timeout period, i.e. the time it takes for the down-counter to underflow, as 128, 512, 1024, or 2048
cycles of the frequency-divided clock set by the IWDTCKS[3:0] bits. The time (number of IWDT-dedicated clock
cycles) it takes to underflow after a refresh operation is determined by the combination of the IWDTCKS[3:0] bits and
IWDTTOPS[1:0] bits.
For details, see section 22, Independent Watchdog Timer (IWDTa) .
IWDTCKS[3:0] Bits (IWDT Clock Frequency Division Ratio Select)
These bits select, from 1/1, 1/16, 1/32, 1/64, 1/128, and 1/256, the division ratio of the prescaler to divide the frequency
of the IWDT-dedicated clock. Using the setting of these bits together with the IWDTTOPS[1:0] bit setting, the IWDT
counting period can be set from 128 to 524288 IWDT-dedicated clock cycles.
For details, see section 22, Independent Watchdog Timer (IWDTa) .
IWDTRPES[1:0] Bits (IWDT Window End Position Select)
These bits select the position of the end of the window for the down-counter as 0%, 25%, 50%, or 75% of the value being
counted by the counter. The value of the window end position must be smaller than the value of the window start position
(window start position > window end position). If the value for the window end position is greater than the value for the
window start position, only the value for the window start position is effective.
The counter values corresponding to the settings for the start and end positions of the window in the IWDTRPSS[1:0]
and IWDTRPES[1:0] bits vary with the setting of the IWDTTOPS[1:0] bits.
For details, refer to section 22, Independent Watchdog Timer (IWDTa) .
IWDTRPSS[1:0] Bits (IWDT Window Start Position Select)
These bits select the position where the window for the down-counter starts as 25%, 50%, 75%, or 100% of the value
being counted (the point at which counting starts is 100% and the point at which an underflow occurs is 0%). The
interval between the positions where the window starts and ends becomes the period in which refreshing is possible, and
refreshing is not possible outside this period.
For details, refer to section 22, Independent Watchdog Timer (IWDTa) .
IWDTRSTIRQS Bit (IWDT Reset Interrupt Request Select)
The setting of this bit selects the operation on an underflow of the down-counter or generation of a refresh error. Either
an independent watchdog timer reset or a non-maskable interrupt request is selectable.
For details, refer to section 22, Independent Watchdog Timer (IWDTa) .
IWDTSLCSTP Bit (IWDT Sleep Mode Count Stop Control)
This bit selects whether to stop counting when entering sleep, software standby, or deep sleep mode.
For details, see section 22, Independent Watchdog Timer (IWDTa) .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
7. Option-Setting Memory (OFSM)
Page 108 of 1041