Renesas RX100 Series User Manual page 428

RX13T Group
(b) Register Operation
In complementary PWM mode, nine registers (compare registers, buffer registers, and temporary registers) are used to
control the duty ratio for the PWM output. Figure 19.47 shows an example of operation in complementary PWM mode
(MTU3 and MTU4).
MTU3.TGRB, MTU4.TGRA, and MTU4.TGRB are constantly compared with the counters to generate PWM
waveforms. When these registers match the counter, the value set in the OLSN and OLSP bits in the timer output control
register (TOCR1A) is output from the PWM output pin.
MTU3.TGRD, MTU4.TGRC, and MTU4.TGRD are buffer registers for these compare registers.
When the double buffer function is used, MTU3.TGRE, MTU4.TGRE, and MTU4.TGRF are also used as buffer
registers B. For details of double buffer operation, refer to section 19.3.8 (2) (r), Double Buffer Function in
Complementary PWM Mode .
Data in a compare register can be changed by writing new data to the corresponding buffer register. The buffer registers
can be read or written at any time.
When modifying data in a buffer register, write to MTU4.TGRD last and enable data transfer from the buffer register to
a temporary register. At this time, transfer from the TCBRA register and MTU3.TGRC register, which operate as buffer
registers for the timer period registers, to temporary registers is also enabled. Data is transferred to all five temporary
registers at the same time.
When transfer is enabled in the Ta interval, data written to a buffer register is transferred to the temporary register. The
data is not transferred to the temporary register in the Tb1 and Tb2 intervals. Data enabled for transfer in this interval is
transferred to the temporary register at the end of this interval.
The value transferred to a temporary register is transferred to the compare register at the end of the Tb1 interval (when
matches MTU3.TGRA while TCNTSA is counting up), or at the end of the Tb2 interval (when matches 0000h while
TCNTSA is counting down). The timing for transfer from the temporary register to the compare register can be
selected with bits MD[3:0] in the timer mode register 1 (TMDR1). Figure 19.47 shows an example in which the
trough is selected for the transfer timing.
In the Tb interval in which data is not transferred to the temporary register (Tb1 in Figure 19.47 ), the temporary
register has the same function as the compare register and is compared with the counter. In this interval, therefore, there
are two compare match registers for one output phase; the compare register contains the pre-change data and the
temporary register contains new data. In this interval, three counters MTU3.TCNT, MTU4.TCNT, and TCNTSA and two
registers (compare register and temporary register) are compared, and PWM output is controlled accordingly.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Page 428 of 1041