Detection Of Bus Collisions - Renesas RX100 Series User Manual

RX13T Group
23.10.4

Detection of Bus Collisions

Detection of bus collisions operate for cases where output of the Break Field low width and transmission of data are in
progress when the ESMER.ESME bit and the SCI.TE bit are set to 1.
Figure 23.68 shows an example of operations with bus collision detection. Signals output through TXDX12 and input
through RXDX12 are sampled with the bus collision detection clock set with the CR2.BCCS[1:0] bits as the sampling
clock, and the STR.BCDF flag is set to 1 if the signals fail to match three times in a row. An SCIX2 interrupt is also
generated if the value of the ICR.BCDIE bit is 1.
Base clock
TXDX12 output signal
RXDX12 input signal
Bus collision clock
TXDX12 output signal
RXDX12 input signal
STR.BCDF
The above diagram assumes the following:
ESMER: ESME = 1
CR2: BCCS[1:0] = 01b
PCR: TXDXPS = 0, RXDXPS = 0
ICR: BCDIE = 1
Figure 23.68 Example of Operations with Bus Collision Detection
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
CR2.BCCS[1:0]
No division
Division by 2
Divider
Division by 4
C
D Q
23. Serial Communications Interface (SCIg, SCIh)
Bus collision detection clock
C C
D Q D
Match-
Q
detection
circuit
Signals not
matching 3 times
confirms a bus
collision.
Write 1 to
STCR.BCDCL
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