Master Reception (Simple I 2 C Mode) - Renesas RX100 Series User Manual

RX13T Group
23.7.6 Master Reception (Simple I
Figure 23.54 shows an example of operations in simple I
showing the procedure for master reception.
The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts).
2
In simple I C mode, the transmit data empty interrupt (TXI) is generated when communication of one frame is
completed, unlike the TXI interrupt request generation timing during clock synchronous transmission.
Start
condition
SSCLn
SSDAn
RXI interrupt flag
1
*
(IRn in the ICU )
TXI interrupt flag
1
*
(IRn in the ICU )
STI interrupt flag
1
*
(IRn in the ICU )
Generation of STI interrupt request
Note1. Refer to section 14, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.
Figure 23.54 Example of Operations for Master Reception in Simple I
(with 7-Bit Slave Addresses, Transmission Interrupts, and Reception Interrupts in Use)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Slave address (7 bits)
R
D7 D6 D1 D0
RXI is assumed to have been disabled by
setting SCR.RIE = 0.
Generation of TXI interrupt request
Acceptance of STI interrupt request
23. Serial Communications Interface (SCIg, SCIh)
2
C Mode)
2
C mode master reception and Figure 23.55 is a flowchart
Received data
ACK D7 D6
Generation of RXI interrupt request
Acceptance of TXI interrupt request
2
Stop condition
D1 D0
NACK
Generation of TXI interrupt request
Generation of STI interrupt request
C-bus Mode
Page 687 of 1041