Voltage Monitoring 1 Circuit Control Register 0 (Lvd1Cr0) - Renesas RX100 Series User Manual

RX13T Group
8.2.7

Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0)

Address(es): 0008 C29Ah
b7 b6
LVD1R
LVD1RI
N
1 0
Value after reset:
x: Undefined
Bit Symbol Bit Name
b0 LVD1RIE Voltage Monitoring 1 Interrupt/Reset
Enable
b1 — Reserved
b2 LVD1CMPE Voltage Monitoring 1 Circuit Comparison
Result Output Enable
b3 — Reserved
b5, b4 — Reserved
b6 LVD1RI Voltage Monitoring 1 Circuit Mode Select
b7 LVD1RN Voltage Monitoring 1 Reset Negation
Select
Note: Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
LVD1RIE Bit (Voltage Monitoring 1 Interrupt/Reset Enable)
The LVD1RIE bit is enabled when the LVCMPCR.LVD1E bit is set to 1 (voltage detection 1 circuit enabled) and the
LVD1CMPE bit is set to 1 (voltage monitoring 1 circuit comparison results output enabled).
Ensure that neither a voltage monitoring 1 reset nor a voltage monitoring 1 non-maskable interrupt is generated during
programming or erasure of the flash memory.
LVD1RN Bit (Voltage Monitoring 1 Reset Negation Select)
If the LVD1RN bit is to be set to 1 (negation follows a stabilization time after assertion of the voltage monitoring 1 reset),
set the LOCOCR.LCSTP bit to 0 (LOCO is operating). Furthermore, if a transition to software standby mode, the only
possible value for the LVD1RN bit is 0 (negation follows a stabilization time after VCC > Vdet1 is detected). Do not set
the LVD1RN bit to 1 (negation follows a stabilization time after assertion of the voltage monitoring 1 reset).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
LVD1C
— — —
MPE
0 0 X 0
b1 b0
LVD1RI
—
E
0 0
Description
0: Disabled
1: Enabled
This bit is read as 0. The write value should be 0.
0: Voltage monitoring 1 circuit comparison results output
disabled
1: Voltage monitoring 1 circuit comparison results output
enabled
The read value is undefined. The write value should be 0. R/W
These bits are read as 0. The write value should be 0.
0: Voltage monitoring 1 interrupt occurs when the voltage
passes Vdet1
1: Voltage monitoring 1 reset occurs when the voltage
falls below Vdet1
0: Negation follows a stabilization time (tLVD1) after
VCC > Vdet1 is detected.
1: Negation follows a stabilization time (tLVD1) after
assertion of the voltage monitoring 1 reset.
8. Voltage Detection Circuit (LVDAb)
Page 121 of 1041
R/W
R/W
R/W
R/W
R/W
R/W
R/W