Renesas RX100 Series User Manual page 749

RX13T Group
NACKF Flag (NACK Detection Flag)
[Setting condition]
 When acknowledge is not received (NACK is received) from the receive device in transmit mode with the
ICFER.NACKE bit set to 1 (transfer abort enabled)
[Clearing conditions]
 When 0 is written to the NACKF bit after reading NACKF = 1
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Note: When the NACKF flag is set to 1, the RIIC aborts data transmission/reception. Writing to the ICDRT register in
transmit mode or reading from the ICDRR register in receive mode with the NACKF flag set to 1 does not enable
data transmit/receive operation. To restart data transmission/reception, set the NACKF flag to 0.
RDRF Flag (Receive Data Full Flag)
[Setting conditions]
 When receive data has been transferred from the ICDRS register to the ICDRR register
This flag is set to 1 at the rising edge of the eighth or ninth SCL clock cycle (selected by the ICMR3.RDRFS bit)
 When the received slave address matches after a start condition (or a restart condition) is detected with the
ICCR2.TRS bit set to 0
[Clearing conditions]
 When 0 is written to the RDRF bit after reading RDRF = 1
 When data is read from the ICDRR register
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
TEND Flag (Transmit End Flag)
[Setting condition]
 At the rising edge of the ninth SCL clock cycle while the TDRE flag is 1
[Clearing conditions]
 When 0 is written to the TEND bit after reading TEND = 1
 When data is written to the ICDRT register
 When a stop condition is detected
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
TDRE Flag (Transmit Data Empty Flag)
[Setting conditions]
 When data has been transferred from the ICDRT register to the ICDRS register and the ICDRT register becomes
empty
 When the ICCR2.TRS bit is set to 1
 When the received slave address matches while the TRS bit is 1
[Clearing conditions]
 When data is written to the ICDRT register
 When the ICCR2.TRS bit is set to 0
 When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Note: When the NACKF flag is set to 1 while the ICFER.NACKE bit is 1, the RIIC aborts data transmission/reception.
Here, if the TDRE flag is 0 (next transmit data has been written), data is transferred to the ICDRS register and the
ICDRT register becomes empty at the rising edge of the ninth clock cycle, but the TDRE flag is not set to 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2
24. I C-bus Interface (RIICa)
Page 749 of 1041