Serial Data Transmission (Clock Synchronous Mode) - Renesas RX100 Series User Manual

RX13T Group
23.5.4

Serial Data Transmission (Clock Synchronous Mode)

Figure 23.24 , Figure 23.25 , and Figure 23.26 show an example of the operation for serial transmission in clock
synchronous mode.
In serial data transmission, the SCI operates as described below.
1. The SCI transfers data from TDR to TSR when data is written to TDR in the TXI interrupt handling routine. The
TXI interrupt request at the beginning of transmission is generated when the TE bit in the SCR register is set to 1
after the TIE bit in the SCR register is set to 1 or when these 2 bits are set to 1 simultaneously by a single
instruction.
2. After transferring data from the TDR register to the TSR register, the SCI starts transmission. When the SCR.TIE
bit is set to 1 at this time, a TXI interrupt request is generated. Continuous transmission is enabled by writing the
next transmit data to the TDR register in this TXI interrupt handling routine before transmission of the current
transmit data has finished. When TEI interrupt requests are in use, set the SCR.TIE bit to 0 (a TXI interrupt request
is disabled) and the SCR.TEIE bit to 1 (a TEI interrupt request is enabled) after the last of the data to be transmitted
are written to the TDR register from the handling routine for TXI requests.
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when clock output mode has been
specified and in synchronization with the input clock when use of an external clock has been specified. Output of
the clock signal is suspended until the input CTS signal is at the low level while the CTSE bit in the SPMR register
is 1 (CTS function is enabled).
4. The SCI checks for updating of (writing to) the TDR register at the time of the last bit output.
5. When TDR is updated, the next transmit data is transferred from the TDR register to the TSR register, and serial
transmission of the next frame is started.
6. If the TDR register is not updated, set the SSR.TEND flag to 1 and the TXDn pin retains the output state of the last
bit. If the TEIE bit in the SCR register is 1 at this time, a TEI interrupt request is generated. The SCKn pin is held
high.
Figure 23.27 shows a sample flowchart of serial data transmission.
Transmission will not start while a receive error flag (ORER, FER, or PER in the SSR register) is set to 1. Be sure to set
the receive error flags to 0 before starting transmission. Note that setting the RE bit in the SCR register to 0 does not clear
the receive error flags.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
23. Serial Communications Interface (SCIg, SCIh)
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