Renesas RX100 Series User Manual page 585

RX13T Group
Table 23.3 Functions of SCI Channels
Item
Asynchronous mode
Clock synchronous mode
Smart card interface mode
2
Simple I C mode
Simple SPI mode
Extended serial mode
MTU clock input
RXDn/
SSCLn/
SMISOn
TXDn/
SSDAn/
SMOSIn
RTSn#/
CTSn#/
SSn#
SCKn
RDR:
RDRH:
RDRL:
RSR:
TDR:
TDRH:
TDRL:
TSR:
SMR:
SCR:
SSR:
Figure 23.1 Block Diagram of SCIg (SCI1 and SCI5)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
SCI1
Available
Available
Available
Available
Available
Not available
Available
RDRH TDRH
RDR(L) TDR(L)
RSR TSR
Parity addition
Parity check
External clock
Receive data register
Receive data register H
Receive data register L
Receive shift register
Transmit data register
Transmit data register H
Transmit data register L
Transmit shift register
Serial mode register
Serial control register
Serial status register
23. Serial Communications Interface (SCIg, SCIh)
SCI5
Available
Available
Available
Available
Available
Not available
Available
Module data bus
SMR
SCR
SSR
Clock
SCMR
SEMR
SNFR
SIMR1
SIMR2
SIMR3
SISR
SPMR
Transmission
and reception
control
SCMR:
BRR:
MDDR:
SEMR:
SNFR:
SIMR1:
SIMR2:
SIMR3:
SISR:
SPMR:
SCI12
Available
Available
Available
Available
Available
Available
Available
BRR
MDDR
Baud rate
generator
MTIOC1A
MTIOC2A
TEI interrupt request
TXI interrupt request
RXI interrupt request
ERI interrupt request
Smart card mode register
Bit rate register
Modulation duty register
Serial extended mode register
Noise filter setting register
2
I C mode register 1
2
I C mode register 2
2
I C mode register 3
2
I C status register
SPI mode register
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PCLK
PCLK/4
PCLK/16
PCLK/64
MTU