Active Level Setting Register 1 (Alr1) - Renesas RX100 Series User Manual

RX13T Group
refer to section 20.3.7, Recover from High-Impedance State .
20.2.6

Active Level Setting Register 1 (ALR1)

Address(es): POE.ALR1 0008 C4DAh
b15 b14
— —
0 0
Value after reset:
Bit Symbol
b0 OLSG0A
b1 OLSG0B
b2 OLSG1A
b3 OLSG1B
b4 OLSG2A
b5 OLSG2B
b6 —
b7 OLSEN
b15 to b8 —
Note 1. Can be modified only once after a reset.
The ALR1 register specifies the active levels of the MTU outputs for detection of simultaneous conduction of those
outputs as reflected in the OCSR1 register.
OLSG0A Bit (MTIOC3B Pin Active Level Setting)
This bit sets the active level of the MTIOC3B output. Specifically, setting the OLSG0A bit to 0 sets the low level and to
1 sets the high level as the active level for detection of simultaneous conduction.
OLSG0B Bit (MTIOC3D Pin Active Level Setting)
This bit sets the active level of the MTIOC3D output. Specifically, setting the OLSG0B bit to 0 sets the low level and to
1 sets the high level as the active level for detection of simultaneous conduction.
OLSG1A Bit (MTIOC4A Pin Active Level Setting)
This bit sets the active level of the MTIOC4A output. Specifically, setting the OLSG1A bit to 0 sets the low level and to
1 sets the high level as the active level for detection of simultaneous conduction.
OLSG1B Bit (MTIOC4C Pin Active Level Setting)
This bit sets the active level of the MTIOC4C output. Specifically, setting the OLSG1B bit to 0 sets the low level and to
1 sets the high level as the active level for detection of simultaneous conduction.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — —
0 0 0 0
Bit Name
MTIOC3B Pin Active Level Setting
MTIOC3D Pin Active Level Setting
MTIOC4A Pin Active Level Setting
MTIOC4C Pin Active Level Setting
MTIOC4B Pin Active Level Setting
MTIOC4D Pin Active Level Setting
Reserved
Active Level Setting Enable
Reserved
b9 b8 b7 b6
OLSG2
— — OLSEN —
0 0 0 0
Description
0: Active low
1: Active high
0: Active low
1: Active high
0: Active low
1: Active high
0: Active low
1: Active high
0: Active low
1: Active high
0: Active low
1: Active high
This bit is read as 0. The write value should be 0.
0: Disabled
1: Enabled
These bits are read as 0. The write value should be 0.
20. Port Output Enable 3 (POE3C)
b5 b4 b3 b2
OLSG2 OLSG1 OLSG1 OLSG0
B A B A
0 0 0 0
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b1 b0
OLSG0
B A
0 0
R/W
1
R/W*
1
R/W*
1
R/W*
1
R/W*
R/W* 1
1
R/W*
R/W
1
R/W*
R/W