Renesas RX100 Series User Manual page 278

RX13T Group
 DTC Index
Address(es): DTCIBR + p × 4
b31 b30
0 0
Value after reset:
b15 b14
0 0
Value after reset:
Bit Symbol
b0 CPUSEL
b1 —
b31 to b2 DTCIADDR[31:2]
When the CPUSEL bit in the DTC index that the obtained sequence number indicates is 1, an interrupt request to the
CPU is generated. At this time, the ICU.DTCERn.DTCE bit becomes 0. From this point, the interrupt request signal from
the request source that is specified in the DTCSQE register is sent to the CPU, but not DTC. After completion of CPU
interrupt processing, set the ICU.DTCERn.DTCE bit to 1 to enable DTC transfer request for starting the next sequence
transfer.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b29 b28 b27 b26
0 0 0 0
b13 b12 b11 b10
DTCIADDR[15:2]
0 0 0 0
Bit Name
Sequence Transfer/CPU Interrupt
Select
Reserved
Transfer Information Table Address
b25 b24 b23 b22
DTCIADDR[31:16]
0 0 0 0
b9 b8 b7 b6
0 0 0 0
Description
0: Continues the sequence transfer (starts the
sequence)
1: Ends the sequence transfer and outputs an interrupt
request to the CPU
Set this bit to 0.
Set the upper 30 bits of the start address of the transfer
information table to these bits. Writing to the upper 4
bits (b31 to b28) is ignored and the values in b31 to b28
become the same value as b27.
16. Data Transfer Controller (DTCb)
b21 b20 b19 b18
0 0 0 0
b5 b4 b3 b2
0 0 0 0
Page 278 of 1041
b17 b16
0 0
b1 b0
CPUSE
—
L
0 0
R/W
—
—
—