Contention Between Overflow/Underflow And Counter Clearing; Contention Between Tcnt Write Operation And Overflow/Underflow - Renesas RX100 Series User Manual

RX13T Group
19.6.17

Contention between Overflow/Underflow and Counter Clearing

If an overflow/underflow and counter clearing occur simultaneously, a TCIVn interrupt (n = 0 to 4) nor a TCIUn
interrupt (n = 1, 2) is not generated and TCNT clearing takes precedence.
Figure 19.136 shows the operation timing when a TGR compare match is specified as the clearing source and TGR is
set to FFFFh.
TCNT count clock
Counter clear signal
TCIV interrupt signal
Figure 19.136 Contention between Overflow and Counter Clearing
19.6.18

Contention between TCNT Write Operation and Overflow/Underflow

If TCNT counts up or down in a TCNT write cycle and an overflow or an underflow occurs, the TCNT write operation
takes precedence. A TCIVn interrupt (n = 0 to 4) nor a TCIUn interrupt (n = 1, 2) is not generated.
Figure 19.137 shows the operation timing when there is contention between TCNT write operation and overflow.
TCNT count clock
TCIV interrupt signal
Figure 19.137 Contention between TCNT Write Operation and Overflow
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
PCLKB
TCNT
FFFFh
Disabled
PCLKB
TCNT FFFFh
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
0000h
Written by CPU
TCNT write data
Disabled
M
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