Flash Status Register 1 (Fstatr1) - Renesas RX100 Series User Manual

RX13T Group
31.4.20

Flash Status Register 1 (FSTATR1)

Address(es): FLASH.FSTATR1 007F FF8Bh
b7 b6
EXRDY FRDY
0 0
Value after reset:
Bit Symbol Bit Name
b0 — Reserved
b1 DRRDY Data Read Ready Flag
b2 — Reserved
b5 to b3 — Reserved
b6 FRDY Flash Ready Flag
b7 EXRDY Extra Area Ready Flag
This register is a status register used to confirm the result of executing a software command. Each flag is set to 0 when
the next software command is executed.
DRRDY Flag (Data Read Ready Flag)
This flag is used to check if the valid read data is stored in registers FRBH and FRBL.
When the sequencer stores data read from the flash memory to registers FRBH and FRBL, the DRRDY flag becomes 1.
When issuing the unique ID command with the FCR.DRC bit set to 1, the sequencer ends the read cycle, and the
DRRDY flag becomes 0.
Note that, even if issuing the unique ID command with the FCR.DRC bit set to 0 after reading data from the address set
in registers FEARH and FEARL, the DRRDY flag does not become 1, but the FRDY flag becomes 1.
FRDY Flag (Flash Ready Flag)
This flag is used to confirm whether a software command is executed.
This flag becomes 1 when processing of the executed software command or the forced stop processing is completed, and
this flag becomes 0 when setting the FCR.OPST bit to 0.
Also, an interrupt (FRDYI) is generated when this flag becomes 1.
EXRDY Flag (Extra Area Ready Flag)
This flag is used to confirm whether a software command for the extra area is executed.
This flag is set to 1 when processing of the executed software command is completed, and 0 when the FEXCR.OPST bit
is set to 0.
Also, an interrupt (FRDYI) is generated when this flag becomes 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — — DRRDY
0 0 0 1
b1 b0
—
0 0
Description
This bit is read as 0.
0: No valid data in registers FRBH and FRBL
1: Valid data in registers FRBH and FRBL
This bit is read as 1.
These bits are read as 0.
0: Other than below
1: 00h can be written to the FCR register (processing to
complete the software command).
0: Other than below
1: 00h can be written to the FEXCR register (processing to
complete the software command).
31. Flash Memory (FLASH)
R/W
R
R
R
R
R
R
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