Conditions Leading To Bus Errors - Renesas RX100 Series User Manual

RX13T Group
15.4.3

Conditions Leading to Bus Errors

Table 15.5 lists the type of bus errors for each area in the respective address space.
If an illegal address access error or timeout is detected when no bus error has occurred (bus error status register n
(BERSRn; n = 1 or 2) is cleared), the detected error is reflected on the BERSRn. Once a bus error occurs, no subsequent
bus errors are reflected in the register unless the register is cleared.
If bus errors are simultaneously caused by two or more bus masters, error information of only one bus master is reflected.
Once a bus error occurs, the status is retained until the BERSRn register is cleared.
Table 15.5 Type of Bus Errors
Address
0000 0000h to 0007 FFFFh
0008 0000h to 0008 7FFFh
0008 8000h to 0009 FFFFh
000A 0000h to 000B FFFFh
000C 0000h to 000F FFFFh
0010 0000h to 00FF FFFFh
0100 0000h to 07FF FFFFh
0800 0000h to 0FFF FFFFh
1000 0000h to 7FFF FFFFh
8000 0000h to FFFF FFFFh
—: A bus error does not result.
Δ: A bus error may or may not result.
○: A bus error results.
Note: The capacity of the RAM, data flash, and ROM differs depending on the product. For details, refer to section 30, RAM, and
section 31, Flash Memory (FLASH).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Type of Area
Memory bus 1
Internal peripheral bus 1
Internal peripheral bus 2
Internal peripheral bus 3
Reserved area
Internal peripheral bus 6
Reserved area
Reserved area
Reserved area
Memory bus 2
Type of Error
Illegal Address Access Timeout
—
—
Δ
Δ
○
Δ
○
—
○
—
15. Buses
—
—
Δ
—
—
—
—
—
—
—
Page 243 of 1041