Timer Interrupt Skipping Set Register 1 (Titcr1A) - Renesas RX100 Series User Manual

RX13T Group
19.2.38

Timer Interrupt Skipping Set Register 1 (TITCR1A)

Address(es): MTU.TITCR1A 0009 5230h
b7 b6
T3AEN T3ACOR[2:0]
Value after reset: 0 0
Bit Symbol
b2 to b0 T4VCOR[2:0]
b3 T4VEN
b6 to b4 T3ACOR[2:0]
b7 T3AEN
Note 1. When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed.
Before changing the interrupt skipping count, be sure to set the TITCR1A.T3AEN and TITCR1A.T4VEN bits to 0 to clear the
skipping counter (TITCNT1A).
The TITCR1A register enables or disables interrupt skipping and specify the interrupt skipping count. This setting is
valid only while the TITMRA.TITM bit is set to 0; when the TITMRA.TITM bit is set to 1, the setting in the TITCR1A
register is cleared.
Table 19.42 Setting of Interrupt Skipping Count by T4VCOR[2:0] Bits
Bit 2 Bit 1
T4VCOR[2] T4VCOR[1]
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Table 19.43 Setting of Interrupt Skipping Count by T3ACOR[2:0] Bits
Bit 6 Bit 5
T3ACOR[2] T3ACOR[1]
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
T4VEN T4VCOR[2:0]
0 0 0 0
Bit Name
TCIV4 Interrupt Skipping Count
Setting
T4VEN
TGIA3 Interrupt Skipping Count
Setting
T3AEN
Bit 0
T4VCOR[0] Description
0 Does not skip TCIV4 interrupts.
1 Sets the TCIV4 interrupt skipping count to 1.
0 Sets the TCIV4 interrupt skipping count to 2.
1 Sets the TCIV4 interrupt skipping count to 3.
0 Sets the TCIV4 interrupt skipping count to 4.
1 Sets the TCIV4 interrupt skipping count to 5.
0 Sets the TCIV4 interrupt skipping count to 6.
1 Sets the TCIV4 interrupt skipping count to 7.
Bit 4
T3ACOR[0] Description
0 Does not skip TGIA3 interrupts.
1 Sets the TGIA3 interrupt skipping count to 1.
0 Sets the TGIA3 interrupt skipping count to 2.
1 Sets the TGIA3 interrupt skipping count to 3.
0 Sets the TGIA3 interrupt skipping count to 4.
1 Sets the TGIA3 interrupt skipping count to 5.
0 Sets the TGIA3 interrupt skipping count to 6.
1 Sets the TGIA3 interrupt skipping count to 7.
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
0 0
Description
These bits specify the TCIV4 interrupt skipping count within
1
the range from 0 to 7.*
For details, refer to Table 19.42.
0: TCIV4 interrupt skipping disabled
1: TCIV4 interrupt skipping enabled
These bits specify the TGIA3 interrupt skipping count within
1
the range from 0 to 7.*
For details, refer to Table 19.43.
0: TGIA3 interrupt skipping disabled
1: TGIA3 interrupt skipping enabled
R/W
R/W
R/W
R/W
R/W
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