Contention Between Buffer Register Write Operation And Input Capture - Renesas RX100 Series User Manual

RX13T Group
19.6.11

Contention between Buffer Register Write Operation and Input Capture

If an input capture signal is generated in the buffer register write cycle, the buffer operation takes precedence and the
buffer register write operation is not performed.
Figure 19.131 shows the timing in this case.
Input capture signal
Buffer register
Figure 19.131 Contention between Buffer Register Write Operation and Input Capture
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
PCLKB
TCNT
TGR
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Written by CPU
N
M N
M
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