Renesas RX100 Series User Manual page 397

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(b) When TGR is an Input Capture Register

Figure 19.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer

operation has been designated for TGRA and TGRC.

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as

the MTIOCnA pin input capture input edge. (n = 0 to 4)

As buffer operation has been set, when the TCNT value is transferred to TGRA upon occurrence of input capture A, the

value previously stored in TGRA is simultaneously transferred to TGRC.

Figure 19.18

Example of Buffer Operation (2) (n = 0 to 4,)

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

19. Multi-Function Timer Pulse Unit 3 (MTU3c)

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