Oscillation Stop Detection Interrupts - Renesas RX100 Series User Manual

RX13T Group
Note: On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation
circuit must be removed on the user system to allow the return of oscillation.
Figure 9.5 Flow of Recovery from Detection of Oscillator Stop
9.4.2

Oscillation Stop Detection Interrupts

An oscillator-stop detection interrupt (OSTDI) request is generated if the oscillation-stop detection flag
(OSTDSR.OSTDF) becomes 1 while the oscillation-stop detection interrupt enable bit (OSTDCR.OSTDIE) is 1
(oscillation stop detection interrupt enabled). At this time, the stop of the main clock oscillator is notified to the port
output enable 3 (POE). On accepting the notification of the oscillation stop, the POE sets the OSTST high-impedance
flag in input level control/status register 6 (ICSR6.OSTSTF) to 1. After the oscillation stop is detected, wait for at least
10 cycles of PCLKB before writing to this ICSR6.OSTSTF flag. When the OSTDSR.OSTDF flag requires clearing, do
so setting the oscillation stop detection interrupt enable bit (OSTDCR.OSTDIE) to 0. Wait for at least two cycles of
PCLKB clock before again setting the OSTDCR.OSTDIE bit to 1. According to the number of cycles for access to read
a given I/O register, wait time longer than two cycles of PCLKB may have to be secured.
The oscillation stop detection interrupt is a non-maskable interrupt. Since non-maskable interrupts are disabled in the
initial state after a reset release, enable the non-maskable interrupts by the software before using oscillation stop
detection interrupts. For details, refer to section 14, Interrupt Controller (ICUb) .
When the PLL detects an oscillation stop and is running at its own oscillation frequency, this indicates the occurrence of
some system failure. An emergency measure should be taken to handle the failure.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Start
Switch to SCKCR3.CKSEL[2:0] = 000b
(LOCO)
Setting OSTDCR.OSTDIE = 0
Reading OSTDSR.OSTDF = 1
Setting OSTDSR.OSTDF = 0
OSTDSR.OSTDF = 0
Yes
Switch to SCKCR3.CKSEL[2:0] = 010b
(main clock oscillator)
End
9. Clock Generation Circuit
Yes
No
Try again?
No
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