Selecting Interrupt Request Destinations - Renesas RX100 Series User Manual

RX13T Group
14.4.3

Selecting Interrupt Request Destinations

Possible settings for the request destination of each interrupt are fixed. That is, settings for request destination other than
those indicated in Table 14.3, Interrupt Vector Table , are not possible. Do not make an interrupt request destination
setting that is not indicated by a "" in Table 14.3 .
If the DTC is selected as the destination for requests from an IRQi pin (i = 0 to 5), be sure to set the IRQMD[1:0] bits in
IRQCRi for that interrupt to select edge detection.
The following describes how to specify the destinations of interrupt requests.
(1) DTC Trigger
Make the following settings for each source while the IERm.IENj bit (m = 02h to 1Fh, j = 0 to 7) is 0.
1. Set the DTC transfer request enable bit in the DTC transfer request enable register (DTCERn.DTCE (n = interrupt
vector number)) for the pertinent source to 1.
After making the above settings, set the IERm.IENj bit to 1.
In addition, set the DTC module start bit (DTCST.DTCST) to 1. The order of making settings for each interrupt and
enabling the DTC module start bit does not matter.
For the DTC setting procedure, refer to section 16.5, DTC Setting Procedure , in section 16, Data Transfer
Controller (DTCb) .
(2) CPU Interrupt Request
If the interrupt request destination is the DTC, the interrupt request is sent to the CPU. Set the IERm.IENj bit (m = 02h to
1Fh, j = 0 to 7) to 1 while the DTC trigger settings described above are in place.
Table 14.4 shows operation when the DTC is the request destination.
Table 14.4 Operation When Starting the DTC
Remaining
Interrupt Number of
Request DISEL Transfer
1
Destination * Operations
3
DTC* 1 ≠ 0
= 0
0 ≠ 0
= 0
Note 1. DISEL for the DTC is set by the DTC.MRB.DISEL bit.
Note 2. When the IRn.IR flag is 1, an interrupt request (DTC transfer request) that is generated again will be ignored.
Note 3. For chain transfer, DTC transfer continues until the last chain transfer ends. Whether a CPU interrupt is generated at the end of
chain transfer, the IRn.IR flag clear timing, and the interrupt request destination after transfer are determined by the state of DISEL
and the remaining transfer count at the end of chain transfer. For the chain transfer, see Table 16.4, Chain Transfer Conditions in
section 16, Data Transfer Controller (DTCb).
The request destination for an interrupt should be changed while the IERm.IENj bit is 0.
When a source is to be changed to an interrupt request or the DTC transfer information is to be changed while a transfer
is not complete (i.e. while the DTCERn.DTCE bit (n = interrupt vector number) has not been cleared) after the settings
described under (1) DTC Trigger have been made, follow the procedure below.
1. For both the source to be withdrawn and the source that will have a new trigger, clear the IENj bits in IERm to 0.
2. Check the state of transfer by the DTC. If transfer is in progress, wait for its completion.
3. Make the settings described under (1) DTC Trigger .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Operation per
2
Request IR*
DTC transfer → Cleared on interrupt acceptance by the CPU
CPU interrupt
DTC transfer → Cleared on interrupt acceptance by the CPU
CPU interrupt
DTC transfer Cleared at the start of DTC data transfer after
reading DTC transfer information
DTC transfer → Cleared on interrupt acceptance by the CPU
CPU interrupt
14. Interrupt Controller (ICUb)
Interrupt Request Destination after Transfer
DTC
The DTCERn.DTCE bit is cleared and the CPU
becomes the destination.
DTC
The DTCERn.DTCE bit is cleared and the CPU
becomes the destination.
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