Register Descriptions; Timer Control Register (Tcr) - Renesas RX100 Series User Manual

RX13T Group
19.2

Register Descriptions

19.2.1

Timer Control Register (TCR)

 MTU0.TCR, MTU1.TCR, MTU2.TCR, MTU3.TCR, MTU4.TCR
Address(es): MTU0.TCR 0009 5300h, MTU1.TCR 0009 5380h, MTU2.TCR 0009 5400h, MTU3.TCR 0009 5200h,
MTU4.TCR 0009 5201h
b7 b6
CCLR[2:0]
0 0
Value after reset:
Bit Symbol
b2 to b0 TPSC[2:0]
b4, b3 CKEG[1:0]
b7 to b5 CCLR[2:0]
x: Don't care
The TCR register controls the TCNT operation for each channel in combination with the TCR2 register. The MTU has a
total of eight TCR registers, one each for MTU0 to MTU4 and three (TCRU, TCRV, and TCRW) for MTU5. TCR values
should be specified only while TCNT operation is stopped.
TPSC[2:0] Bits (Time Prescaler Select)
These bits select the TCNT count clock source. The count clock source can be selected independently for each channel.
Refer to Table 19.6 to Table 19.9 for details.
CKEG[1:0] Bits (Clock Edge Select)
These bits select the clock edge, including the MTIOC1A pin. When the internal clock is counted at both edges, the
count clock period is halved (e.g. PCLKB/4 at both edges = PCLKB/2 at rising edge). If phase counting mode is used on
MTU1 and MTU2, the setting of these bits is ignored and the phase counting mode setting has priority. Internal clock
edge selection is valid when the count clock source is PCLKB/2 or slower. When PCLKB/1 or the overflow/underflow in
another channel is selected for the count clock source, a value can be written to these bits but counter operation compiles
with the initial value.
CCLR[2:0] Bits (Counter Clear Source Select)
These bits select the TCNT counter clearing source. Refer to Table 19.4 and Table 19.5 for details.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
CKEG[1:0] TPSC[2:0]
0 0 0 0
Bit Name
Time Prescaler Select
Clock Edge Select
Counter Clear Source Select
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
0 0
Description
Refer to Table 19.6 to Table 19.9.
b4 b3
0 0: Count at rising edge
0 1: Count at falling edge
1 x: Count at both edges
Refer to Table 19.4 and Table 19.5.
R/W
R/W
R/W
R/W
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