Contention Between Tgr Write Operation And Input Capture - Renesas RX100 Series User Manual

RX13T Group
19.6.10

Contention between TGR Write Operation and Input Capture

If an input capture signal is generated in the TGR write cycle, the input capture operation takes precedence and the TGR
write operation is not performed in MTU0 to MTU4. In MTU5, the TGR write operation is performed and the input
capture signal is generated.
Figure 19.129 and Figure 19.130 show the timing in this case.
Input capture signal
Figure 19.129 Contention between TGR Write Operation and Input Capture (MTU0 to MTU4)
Input capture signal
Figure 19.130 Contention between TGR Write Operation and Input Capture (MTU5)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
PCLKB
TCNT
TGR
PCLKB
TCNT
TGR
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Written by CPU
M
M
Written by CPU
M
TGR write data
N
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