Renesas RX100 Series User Manual page 71

RX13T Group
(2) Pipeline Flow with no Stall
(a) Bypass process
Even when the result of the preceding instruction will be used in a subsequent instruction, the operation processing
between registers is pipelined in by the bypass process.
Figure 2.20 Bypass Process
(b) When WB stages for the memory load and for the operation are overlapped
Even when the WB stages for the memory load and for the operation are overlapped, the operation processing is
pipelined in, because the load data and the operation result can be written to the register at the same timing.
IF
MOV [R1], R2
ADD R5, R3
Figure 2.21 When WB Stages for the Memory Load and for the Operation are Overlapped
(c) When subsequent instruction writes to the same register before the end of memory load
Even when the subsequent instruction writes to the same register before the end of memory load, the operation
processing is pipelined in, because the WB stage for the memory load is canceled.
MOV [R1], R2
Figure 2.22 When Subsequent Instruction Writes to the Same Register before the End of Memory Load
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
ADD R1, R2
IF D
SUB R3, R2 IF
D E M WB
IF D E WB
IF D E M
IF D E
IF D
IF
(mop) add
E WB
Bypass process
D E WB (mop) sub
(mop) load
(mop) add

M WB
(Canceled when the register number
WB
matches either of them)
E WB
D E WB
Executed at the same timing even
when the WB stages are
overlapped
(mop) load
Page 71 of 1041
2. CPU