Renesas RX100 Series User Manual page 12

13.3.2 Vector and Site for Saving the Values in the PC and PSW ...................................................... 193
13.4 Hardware Processing for Accepting and Returning from Exceptions ............................................... 194
13.5 Hardware Pre-Processing .................................................................................................................. 195
13.5.1 Undefined Instruction Exception .............................................................................................. 195
13.5.2 Privileged Instruction Exception .............................................................................................. 195
13.5.3 Floating-Point Exception .......................................................................................................... 195
13.5.4 Reset ......................................................................................................................................... 195
13.5.5 Non-Maskable Interrupt ........................................................................................................... 195
13.5.6 Interrupt .................................................................................................................................... 196
13.5.7 Unconditional Trap ................................................................................................................... 196
13.6 Return from Exception Handling Routine ......................................................................................... 197
13.7 Priority of Exception Events .............................................................................................................. 197
14. Interrupt Controller (ICUb) ........................................................................................................... 198
14.1 Overview ........................................................................................................................................... 198
14.2 Register Descriptions ......................................................................................................................... 200
14.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number) ........................................... 200
14.2.2 Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) .............................................. 201
14.2.3 Interrupt Source Priority Register n (IPRn) (n = interrupt vector number) .............................. 202
14.2.4 Fast Interrupt Set Register (FIR) .............................................................................................. 203
14.2.5 Software Interrupt Generation Register (SWINTR) ................................................................. 204
14.2.6 DTC Transfer Request Enable Register n (DTCERn)
(n = interrupt vector number) ................................................................................................... 205
14.2.7 IRQ Control Register i (IRQCRi) (i = 0 to 5) .......................................................................... 206
14.2.8 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) ............................................................ 207
14.2.9 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) ........................................................... 208
14.2.10 Non-Maskable Interrupt Status Register (NMISR) .................................................................. 209
14.2.11 Non-Maskable Interrupt Enable Register (NMIER) ................................................................ 211
14.2.12 Non-Maskable Interrupt Status Clear Register (NMICLR) ..................................................... 212
14.2.13 NMI Pin Interrupt Control Register (NMICR) ......................................................................... 213
14.2.14 NMI Pin Digital Filter Enable Register (NMIFLTE) ............................................................... 213
14.2.15 NMI Pin Digital Filter Setting Register (NMIFLTC) .............................................................. 214
14.3 Vector Table ...................................................................................................................................... 215
14.3.1 Interrupt Vector Table .............................................................................................................. 215
14.3.2 Fast Interrupt Vector Table ....................................................................................................... 221
14.3.3 Non-maskable Interrupt Vector Table ...................................................................................... 221
14.4 Interrupt Operation ............................................................................................................................ 222
14.4.1 Detecting Interrupts .................................................................................................................. 222
14.4.1.1
14.4.1.2
14.4.2 Enabling and Disabling Interrupt Sources ................................................................................ 225
14.4.3 Selecting Interrupt Request Destinations ................................................................................. 226
Operation of Status Flags for Edge-Detected Interrupts ................................................. 222
Operation of Status Flags for Level-Detected Interrupts ................................................ 224