Renesas RX100 Series User Manual page 331

RX13T Group
Table 19.7 TPSC[2:0], TPSC2[2:0] (MTU1)
TCR2 register
Bit 2 Bit 1
Channel TPSC2[2] TPSC2[1]
MTU1 0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
x: Don't care
Note: This setting has no effect when MTU1 is in phase counting mode.
Table 19.8 TPSC[2:0], TPSC2[2:0] (MTU2)
TCR2 register
Bit 2 Bit 1
Channel TPSC2[2] TPSC2[1]
MTU2 0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
x: Don't care
Note: This setting has no effect when the MTU2 is in phase counting mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
TCR register
Bit 0 Bit 2 Bit 1
TPSC2[0] TPSC[2] TPSC[1]
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 x x
0 x x
1 x x
0 x x
1 x x
0 x x
1 x x
TCR register
Bit 0 Bit 2 Bit 1
TPSC2[0] TPSC[2] TPSC[1]
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 x x
0 x x
1 x x
0 x x
1 x x
0 x x
1 x x
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Bit 0
TPSC[0] Description
0 Internal clock: counts on PCLKB/1
1 Internal clock: counts on PCLKB/4
0 Internal clock: counts on PCLKB/16
1 Internal clock: counts on PCLKB/64
0 External clock: counts on MTCLKA pin input
1 External clock: counts on MTCLKB pin input
0 Internal clock: counts on PCLKB/256
1 Overflow/underflow of MTU2.TCNT
x Internal clock: counts on PCLKB/2
x Internal clock: counts on PCLKB/8
x Internal clock: counts on PCLKB/32
x Internal clock: counts on PCLKB/1024
x Setting prohibited
x Setting prohibited
x Setting prohibited
Bit 0
TPSC[0] Description
0 Internal clock: counts on PCLKB/1
1 Internal clock: counts on PCLKB/4
0 Internal clock: counts on PCLKB/16
1 Internal clock: counts on PCLKB/64
0 External clock: counts on MTCLKA pin input
1 External clock: counts on MTCLKB pin input
0 External clock: counts on MTCLKC pin input
1 Internal clock: counts on PCLKB/1024
x Internal clock: counts on PCLKB/2
x Internal clock: counts on PCLKB/8
x Internal clock: counts on PCLKB/32
x Internal clock: counts on PCLKB/256
x Setting prohibited
x Setting prohibited
x Setting prohibited
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