Non-Maskable Interrupt Status Register (Nmisr) - Renesas RX100 Series User Manual

RX13T Group
14.2.10

Non-Maskable Interrupt Status Register (NMISR)

Address(es): ICU.NMISR 0008 7580h
b7 b6
— —
Value after reset: 0 0
Bit Symbol
b0 NMIST
b1 OSTST
b2 —
b3 IWDTST
b4 LVD1ST
b5 LVD2ST
b7, b6 —
The NMISR register monitors the status of a non-maskable interrupt source. Writing to the NMISR register is ignored.
The setting in the non-maskable interrupt enable register (NMIER) does not affect the status flags in NMISR.
Before the end of the non-maskable interrupt handler, read the NMISR register and confirm the generation status of other
non-maskable interrupts. Be sure to confirm that all of the bits in the NMISR register are set to 0 before the end of the
handler.
NMIST Flag (NMI Status Flag)
This flag indicates the NMI pin interrupt request.
The NMIST flag is read-only, and cleared by the NMICLR.NMICLR bit.
[Setting condition]
 When an edge specified by the NMICR.NMIMD bit is input to the NMI pin
[Clearing condition]
 When 1 is written to the NMICLR.NMICLR bit
OSTST Flag (Oscillation Stop Detection Interrupt Status Flag)
This flag indicates the oscillation stop detection interrupt request.
The OSTST flag is read-only, and cleared by the NMICLR.OSTCLR bit.
[Setting condition]
 When the oscillation stop detection interrupt is generated
[Clearing condition]
 When 1 is written to the NMICLR.OSTCLR bit
IWDTST Flag (IWDT Underflow/Refresh Error Status Flag)
This flag indicates the IWDT underflow/refresh error interrupt request.
The IWDTST flag is read-only, and cleared by the NMICLR.IWDTCLR bit.
[Setting condition]
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
LVD2S LVD1S IWDTS
—
T T T
0 0 0 0
Bit Name
NMI Status Flag
Oscillation Stop Detection
Interrupt Status Flag
Reserved
IWDT Underflow/Refresh
Error Status Flag
Voltage Monitoring 1
Interrupt Status Flag
Voltage Monitoring 2
Interrupt Status Flag
Reserved
b1 b0
OSTST NMIST
0 0
Description
0: NMI pin interrupt is not requested
1: NMI pin interrupt is requested
0: Oscillation stop detection interrupt is not requested
1: Oscillation stop detection interrupt is requested
This bit is read as 0. Writing to this bit has no effect.
0: IWDT underflow/refresh error interrupt is not requested
1: IWDT underflow/refresh error interrupt is requested
0: Voltage monitoring 1 interrupt is not requested
1: Voltage monitoring 1 interrupt is requested
0: Voltage monitoring 2 interrupt is not requested
1: Voltage monitoring 2 interrupt is requested
These bits are read as 0. Writing to these bits has no effect.
14. Interrupt Controller (ICUb)
R/W
R
R
R
R
R
R
R
Page 209 of 1041