Input Level Control/Status Register 6 (Icsr6) - Renesas RX100 Series User Manual

RX13T Group
[Clearing condition]
 By writing 0 to the POE10F flag after reading POE10F = 1
When low-level sampling is set by the POE10M[1:0] bits, the high level needs to be input to the POE10# pin to
write 0 to this flag.
For details, refer to section 20.3.7, Recover from High-Impedance State .
20.2.4

Input Level Control/Status Register 6 (ICSR6)

Address(es): POE.ICSR6 0008 C4DCh
b15 b14
— —
Value after reset: 0 0
Bit Symbol
b8 to b0 —
b9 OSTSTE
b11, b10 —
b12 OSTSTF
b15 to b13 —
Note 1. Can be modified only once after a reset.
Note 2. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
The ICSR6 register controls the oscillation stop high-impedance and indicates status.
OSTSTE Bit (Oscillation Stop High-Impedance Enable)
This bit specifies whether to put the output of the target pin in the high-impedance state when oscillation stop is detected.
OSTSTF Flag (Oscillation Stop Detection Flag)
This flag indicates that a high-impedance request by the oscillation stop has been generated.
When the main clock oscillation stops, this flag is set to 1. To clear this flag, wait for at least 10 cycles of PCLK after this
flag becomes 1 and write 0 to this flag while the OSTDSR.OSTDF flag is 0. Writing 0 to this flag while the
OSTDSR.OSTDF flag is 1 cannot clear this flag. After clearing this flag, confirm that the flag has actually been modified
to 0.
[Setting condition]
 When oscillation stop is detected
[Clearing condition]
 By writing 0 to the OSTSTF flag after reading OSTSTF = 1
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
OSTST
— — —
F
0 0 0 0
Bit Name
Reserved
Oscillation Stop High-Impedance
Enable
Reserved
Oscillation Stop Detection Flag
Reserved
b9 b8 b7 b6
OSTST
— — —
E
0 0 0 0
Description
These bits are read as 0. The write value should be 0.
0: Does not put the output in the high-impedance state when
the oscillation stop is detected.
1: Put the output in the high-impedance state when the
oscillation stop is detected.
These bits are read as 0. The write value should be 0.
0: Indicates that a high-impedance request by oscillation stop
has not been generated.
1: Indicates that a high-impedance request by oscillation stop
has been generated.
These bits are read as 0. The write value should be 0.
20. Port Output Enable 3 (POE3C)
b5 b4 b3 b2
— — — —
0 0 0 0
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b1 b0
— —
0 0
R/W
R/W
1
R/W*
R/W
R/W* 2
R/W