Renesas RX100 Series User Manual page 430

RX13T Group
(c) Initial Setting
In complementary PWM mode, there are nine registers that require initial setting. In addition, there is a register that
specifies whether to generate dead time (it should be used only when dead time generation should be disabled).
Before setting complementary PWM mode with MTU3.TMDR1.MD[3:0] bits, initial values should be set in the
following registers.
The TOCR1A and TOCR2A registers are used to set the PWM output level. MTU3.TGRC operates as the buffer register
for MTU3.TGRA, and should be set with 1/2 the PWM period + dead time Td. The timer period buffer register
(TCBRA) operates as the buffer register for the timer period data register (TCDRA), and should be set with 1/2 the PWM
period. Set dead time Td in the timer dead time data register (TDDRA).
When dead time is not needed, the TDER bit in the timer dead time enable register (TDERA) should be set to 0,
MTU3.TGRC and MTU3.TGRA should be set to 1/2 the PWM carrier period + 1, and TDDRA should be set to 1.
Set the respective initial PWM duty values in three buffer registers A (MTU3.TGRD, MTU4.TGRC, and MTU4.TGRD).
Set three buffer registers B (MTU3.TGRE, MTU4.TGRE, and MTU4.TGRF) only when the double buffer function is
used.
The values set in the five buffer registers excluding TDDRA are transferred to the corresponding compare registers as
soon as complementary PWM mode is set.
Set MTU4.TCNT to 0000h before setting complementary PWM mode.
Table 19.61 Registers and Counters Requiring Initial Setting
Register and Counter
TOCR1A, TOCR2A
MTU3.TGRC
TDDRA
TCBRA
MTU3.TGRD, MTU4.TGRC,
MTU4.TGRD
MTU3.TGRE, MTU4.TGRE,
MTU4.TGRF
MTU4.TCNT
Note: The value set in MTU3.TGRC should be the sum of 1/2 the PWM period set in TCBRA and dead time Td set in TDDRA. When
dead time generation is disabled by TDERA, TGRC should be set to 1/2 the PWM period + 1.
(d) PWM Output Level Setting
In complementary PWM mode, the PWM output level is set with bits OLSN and OLSP in timer output control register 1
(TOCR1A) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2A).
The output level can be set for each of the three positive phases and three negative phases of 6-phase output.
Complementary PWM mode should be cleared before setting or changing output levels.
(e) Dead Time Setting
In complementary PWM mode, dead time can be set for PWM output.
The dead time is set in the timer dead time data register (TDDRA). The value set in TDDRA is used as the MTU3.TCNT
counter start value and creates a non-overlapping interval between MTU3.TCNT and MTU4.TCNT. Complementary
PWM mode should be cleared before changing the contents of TDDRA.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Setting
PWM output level
1/2 PWM period + dead time Td
(1/2 PWM period + 1 when dead time generation is disabled by TDERA)
Dead time Td (1 when dead time generation is disabled by TDERA)
1/2 PWM period
Initial PWM duty ratio value for each phase
Initial PWM duty ratio value for each phase (only when double buffer function is used)
0000h
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
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