Renesas RX100 Series User Manual page 52

RX13T Group
 Rounding towards –: An inexact result is rounded to the nearest available value in the direction of negative
infinity.
(1) Rounding to the nearest value is specified as the default mode and returns the most accurate value.
(2) Modes such as rounding towards 0, rounding towards +, and rounding towards – are used to ensure precision
when interval arithmetic is employed.
CV Flag (Invalid Operation Cause Flag), CO Flag (Overflow Cause Flag),
CZ Flag (Division-by-Zero Cause Flag), CU Flag (Underflow Cause Flag),
CX Flag (Inexact Cause Flag), and CE Flag (Unimplemented Processing Cause Flag)
Floating-point exceptions include the five specified in the IEEE754 standard, namely overflow, underflow, inexact,
division-by-zero, and invalid operation. For a further floating-point exception that is generated upon detection of
unimplemented processing, the corresponding flag (CE) is set to 1.
 The bit that has been set to 1 is cleared to 0 when the FPU instruction is executed.
 When 0 is written to the bit by the MVTC and POPC instructions, the bit is set to 0; the bit retains the previous value
when 1 is written by the instruction.
DN Bit (0 Flush Bit of Denormalized Number)
When this bit is set to 0, a denormalized number is handled as a denormalized number. When this bit is set to 1, a
denormalized number is handled as 0.
EV Bit (Invalid Operation Exception Enable), EO Bit (Overflow Exception Enable),
EZ Bit (Division-by-Zero Exception Enable), EU Bit (Underflow Exception Enable), and
EX Bit (Inexact Exception Enable)
When any of five floating-point exceptions specified in the IEEE754 standard is generated by the floating-point
operation instruction, the bit decides whether the CPU will start handling the exception. When the bit is set to 0, the
exception handling is masked; when the bit is set to 1, the exception handling is enabled.
FV Flag (Invalid Operation Flag), FO Flag (Overflow Flag), FZ Flag (Division-by-Zero Flag),
FU Flag (Underflow Flag), and FX Flag (Inexact Flag)
While the exception handling enable bit (Ej) is 0 (exception handling is masked), if any of five floating-point exceptions
specified in the IEEE754 standard is generated, the corresponding bit is set to 1.
 When Ej is 1 (exception handling is enabled), the value of the flag remains.
 When the corresponding flag is set to 1, it remains 1 until it is cleared to 0 by software. (accumulation flag)
FS Flag (Floating-Point Error Summary Flag)
This bit reflects the logical OR of the FU, FZ, FO, and FV flags.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2. CPU
Page 52 of 1041