Clock Generation Circuit; Overview - Renesas RX100 Series User Manual

RX13T Group
9.

Clock Generation Circuit

9.1

Overview

This MCU incorporates a clock generation circuit.
Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock
generation circuit.
Table 9.1 Specifications of Clock Generation Circuit
Item
Uses
1
Operating frequencies*
3
Main clock oscillator*
PLL circuit
High-speed on-chip oscillator
(HOCO)
Low-speed on-chip oscillator
(LOCO)
IWDT-dedicated on-chip oscillator Oscillation frequency: 15 kHz
Note 1. The maximum operating frequency in high-speed operating mode. For the maximum operating frequency in the other operating
modes, refer to section 11.2.5, Operating Power Control Register (OPCCR).
Note 2. The relationship of frequencies must be set as follows. ICLK: FCLK, PCLKB, and PCLKD = 1: N (N is an integer).
Note 3. When oscillating the PLL at 32 MHz, the frequency of the main clock oscillator is limited to 8 or 16 MHz.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Specification
 Generates the system clock (ICLK) to be supplied to the CPU, DTC, ROM, and RAM.
 Generates the peripheral module clocks (PCLKB, and PCLKD) to be supplied to peripheral
modules.
The peripheral module clock PCLKD is for the S12AD and PCLKB is for other modules.
 Generates the FlashIF clock (FCLK) to be supplied to the FlashIF.
 Generates the CAC clock (CACCLK) to be supplied to the CAC.
 Generates the IWDT-dedicated low-speed clock (IWDTCLK) to be supplied to the IWDT.
 ICLK: 32 MHz (max)*
2
 PCLKB: 32 MHz (max)
 PCLKD: 32 MHz (max)
 FCLK: 1 to 32 MHz (for programming and erasing the ROM and E2 DataFlash)
32 MHz (max) (for reading from the E2 DataFlash)
 CACCLK: Same frequency as each oscillator
 IWDTCLK: 15 kHz
 Resonator frequency: 1 to 20 MHz
 External clock input frequency: 20 MHz (max)
 Connectable resonator or additional circuit: ceramic resonator, crystal
 Connection pins: EXTAL, XTAL
 Oscillation stop detection function:
When an oscillation stop is detected with the main clock, the system clock source is switched to
LOCO and MTU output can be forcedly driven to the high-impedance.
 Drive capacity switching function
 Input clock source: Main clock
 Input pulse frequency division ratio: Selectable from 1, 2, and 4
 Input frequency: 4 to 8 MHz
 Frequency multiplication ratio: Selectable from 4 to 8 (increments of 0.5)
 VCO oscillation frequency: 24 to 32 MHz
Oscillation frequency: 32 MHz
Oscillation frequency: 4 MHz
9. Clock Generation Circuit
Page 129 of 1041