Renesas RX100 Series User Manual page 338

RX13T Group
 MTU5.TIORU, MTU5.TIORV, MTU5.TIORW
Address(es): MTU5.TIORU 0009 5486h, MTU5.TIORV 0009 5496h, MTU5.TIORW 0009 54A6h
b7 b6
— —
0 0
Value after reset:
Bit Symbol
b4 to b0 IOC[4:0]
b7 to b5 —
The TIOR register controls the TGR register. The MTU has a total of 11 TIOR registers, two each for MTU0, MTU3,
and MTU4, one each for MTU1 and MTU2, and three (MTU5.TIORU/TIORV/TIORW) for MTU5. The TIOR register
should be set when the TMDR register setting is normal mode, PWM mode, or phase counting mode.
Note that TIOR is affected by the TMDR1 setting.
The initial output specified by TIOR is valid when the counter is stopped (the CSTn bit in TSTRA is set to 0). Note also
that, in PWM mode 2, the output at the point at which the counter becomes 0000h is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer
register.
Table 19.13 TIORH (MTU0)
Bit 7 Bit 6 Bit 5
IOB[3] IOB[2] IOB[1]
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 1 x
x: Don't care
Note 1. When PCLKB/1 is selected as the count clock for MTU1, MTU0 input capture is not generated. Do not select PCLKB/1 as the
count clock for MTU1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— IOC[4:0]
0 0 0 0
Bit Name Description
I/O Control C Refer to the following table.
MTU5.TIORU, MTU5.TIORV, MTU5.TIORW: Table 19.29
Reserved These bits are read as 0. The write value should be 0.
Bit 4 Description
IOB[0] TGRB Register Function
0 Output compare register
1
0
1
0
1
0
1
0 Input capture register
1
x
x
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
0 0
MTIOC0B Pin Function
Output prohibited
Initial output is low.
Low output at compare match.
Initial output is low.
High output at compare match.
Initial output is low.
Toggle output at compare match.
Output prohibited
Initial output is high.
Low output at compare match.
Initial output is high.
High output at compare match.
Initial output is high.
Toggle output at compare match.
Input capture at rising edge.
Input capture at falling edge.
Input capture at both edges.
Capture input source is the clock source for counting in MTU1.
Input capture on counting up or down by MTU1.TCNT (LWA = 0) or
MTU1.TCNTLW (LWA = 1).*
1
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R/W
R/W
R/W