Renesas RX100 Series User Manual page 564

RX13T Group
To use the IWDT, the IWDT-dedicated clock (IWDTCLK) should be supplied so that the IWDT operates even if the
peripheral module clock (PCLK) stops. The bus interface and registers operate with PCLK, and the 14-bit counter and
control circuits operate with IWDTCLK.
Figure 22.1 is a block diagram of the IWDT.
Clock
frequency
divider
IWDTCLK
IWDTCLK
IWDTCLK/16
IWDTCLK/32
IWDTCLK/64
IWDTCLK/128
IWDTCLK/256
Option function select register 0
(OFS0)
Figure 22.1 IWDT Block Diagram
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
IWDT control circuit
Internal peripheral bus
22. Independent Watchdog Timer (IWDTa)
Interrupt request (WUNI)
IWDT reset output
14-bit counter
Count stop control output
in sleep mode
IWDTRR: IWDT refresh register
IWDTCR: IWDT control register
IWDTSR: IWDT status register
IWDTRCR: IWDT reset control register
IWDTCSTPR: IWDT count stop control register
Interrupt control circuit
Reset control circuit
Clock control circuit
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