Renesas RX100 Series User Manual page 452

RX13T Group
(3) Interrupt Skipping Function 1 in Complementary PWM Mode
Interrupts TGIA3 (at the crest) and TCIV4 (at the trough) in MTU3 and MTU4 can be skipped up to seven times by
making settings in the TITCR1A register.
Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with
interrupt skipping by making settings in the TBTERA register. For the linkage with buffer registers, refer to description
(c) , Buffer Transfer Control Linked with Interrupt Skipping , below.
A/D converter start requests generated by the A/D converter start request delaying function can also be skipped in
coordination with interrupt skipping by making settings in the MTU4.TADCR register. For the linkage with the A/D
converter start request delaying function, refer to section 19.3.9, A/D Converter Start Request Delaying Function .
The TITCR1A register should be set while interrupt skipping function 1 is selected by setting the TITM bit in the timer
interrupt skipping mode register (TITMRA) to 0, TGIA3 interrupt requests are disabled by setting the MTU3.TIER
register, TCIV4 interrupt requests are disabled by setting the MTU4.TIER register, and a compare match is not
generated. Before changing the skipping count, be sure to set the T3AEN and T4VENbits to 0 to clear the skipping
counter.
(a) Example of Interrupt Skipping Function 1 Setting Procedure
Figure 19.77 shows an example of the interrupt skipping function 1 setting procedure. Figure 19.78 shows the periods
during which interrupt skipping count can be changed.
Interrupt skipping 1
Clear interrupt skipping
Set interrupt skipping mode
Set skipping count and
enable interrupt skipping
<Interrupt skipping>
Figure 19.77 Example of Interrupt Skipping Function 1 Setting Procedure
MTU3.TCNT
MTU4.TCNT
Period during
which skipping
count can be
changed
Figure 19.78 Periods during which Interrupt Skipping Count can be Changed
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
[1] Set bits T3AEN and T4VEN in the timer interrupt skipping set register 1
(TITCR1A) to 0 to clear the skipping counter.
[1]
[2] Set bit TITM in the timer interrupt skipping mode register (TITMRA) to 0
counter
to select interrupt skipping function 1.
[3] Specify the interrupt skipping count within the range from 0 to 7 times in
[2]
bits T3ACOR2 to T3ACOR0 and T4VCOR2 to T4VCOR0 in TITCR1A,
and enable interrupt skipping through bits T3AEN and T4VEN.
Note:
[3]
Period during
which skipping
count can be
changed
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
The setting of TITCR1A must be done while the TGIA3 and TCIV4
interrupt requests are disabled by the settings of MTU3.TIER and
MTU4.TIER under the conditions in which a compare match is not
generated. Before changing the skipping count, be sure to set the
T3AEN and T4VEN bits to 0 to clear the skipping counter.
Period during Period during
which skipping which skipping
count can be count can be
changed changed
MTU3.TCNT
MTU4.TCNT
TCNTSA
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