Receive Data Register H, L, Hl (Rdrh, Rdrl, Rdrhl); Transmit Data Register (Tdr) - Renesas RX100 Series User Manual

RX13T Group
23.2.3

Receive Data Register H, L, HL (RDRH, RDRL, RDRHL)

 Receive Data Register H (RDRH)
Address(es): SCI1.RDRH 0008 A030h, SCI5.RDRH 0008 A0B0h, SCI12.RDRH 0008 B310h
 Receive Data Register L (RDRL)
Address(es): SCI1.RDRL 0008 A031h, SCI5.RDRL 0008 A0B1h, SCI12.RDRL 0008 B311h
 Receive Data Register HL (RDRHL)
Address(es): SCI1.RDRHL 0008 A030h, SCI5.RDRHL 0008 A0B0h, SCI12.RDRHL 0008 B310h
b7 b6
0 0
Value after reset:
RDRH and RDRL are 8-bit registers that store receive data. Use these registers when asynchronous mode and 9-bit data
length are selected.
RDRL is the shadow register of RDR; i.e. access to RDRL is equivalent to access to RDR.
After one frame of data is received, the received data is transferred from the RSR register to these registers, thus allowing
the RSR register to receive the next data.
The RSR, RDRH and RDRL registers have a double-buffered construction to enable continuous reception.
Read RDRH and RDRL should be performed only once in the order from RDRH to RDRL when a receive data full
interrupt (RXI) request is issued. Note that an overrun error occurs when the next frame of data is received before the
received data has been read from RDRL.
The CPU cannot write to the RDRH and RDRL registers. Bits 0 to 7 in RDRH are fixed to 0. These bits are read as 0.
The RDRHL register can be accessed in 16-bit units.
23.2.4

Transmit Data Register (TDR)

Address(es): SCI1.TDR 0008 A023h, SCI5.TDR 0008 A0A3h, SCI12.TDR 0008 B303h
b7 b6
Value after reset: 1 1
TDR is an 8-bit register that stores transmit data.
When the SCI detects that the TSR register is empty, it transfers the transmit data written in the TDR register to the TSR
register and starts transmission.
The double-buffered structures of the TDR register and the TSR register enable continuous serial transmission. If the
next transmit data has already been written to the TDR register when one frame of data is transmitted, the SCI transfers
the written data to the TSR register to continue transmission.
The CPU is able to read from or write to the TDR register at any time. Only write transmit data to the TDR register once
after each instance of the transmit data empty interrupt (TXI).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
RDRH
b5 b4 b3 b2
0 0 0 0
b5 b4 b3 b2
1 1 1 1
23. Serial Communications Interface (SCIg, SCIh)
RDRHL
b1 b0 b7 b6
0 0 0 0
b1 b0
1 1
RDRL
b5 b4 b3 b2
0 0 0 0
Page 589 of 1041
b1 b0
0 0