Input-Level Detection Operation - Renesas RX100 Series User Manual

RX13T Group
20.3.1

Input-Level Detection Operation

If the input conditions set by ICSR1 to ICSR4 occur on the POE0#, POE8#, and POE10# pins, the outputs of the MTU
complementary PWM output pins (MTU3 and MTU4 ), and MTU0 pins are in the high-impedance state. Note however,
that these outputs are still in the high-impedance state even when the MTU functions are not selected for the pins.
(1) Falling Edge Detection
When a change from a high to low level is input to the POE0#, POE8#, and POE10# pins, the outputs of the pins
multiplexed with MTU complementary PWM output pins, and MTU0 pins are in the high-impedance state.
The falling edge is detected after the level is sampled with PCLK. Input a low level for at least one PCLK clock to the
POE0#, POE8#, and POE10# pins.
Figure 20.4 shows a sample timing after the level changes in input to the POE0#, POE8#, and POE10# pins until the
respective pins become high-impedance.
PCLK
POE# pin input
MTIOC3B pin
Note 1. Other pins also become high-impedance at the same timing.
Figure 20.4 Operation when A Falling Edge Detection is Selected
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
20. Port Output Enable 3 (POE3C)
PCLK rising edge
Falling edge detection
High-impedance
*1
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