I 2 C Mode Register 3 (Simr3) - Renesas RX100 Series User Manual

RX13T Group
2
23.2.17 I C Mode Register 3 (SIMR3)
Address(es): SCI1.SIMR3 0008 A02Bh, SCI5.SIMR3 0008 A0ABh, SCI12.SIMR3 0008 B30Bh
b7 b6
IICSCLS[1:0]
0 0
Value after reset:
Bit Symbol
b0 IICSTAREQ
b1 IICRSTAREQ Restart Condition Generation
b2 IICSTPREQ
b3 IICSTIF
b5, b4 IICSDAS[1:0]
b7, b6 IICSCLS[1:0]
Note 1. Generate a start condition only when the SSCLn and SSDAn pins are both high (the corresponding bits in the corresponding
PIDR registers are 1).
Note 2. Generate a restart or stop condition only when the SSCLn pin is low (the corresponding bit in the PIDR register is 0).
Note 3. Do not set more than one from among the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits to 1 at a given time.
Note 4. Execute the generation of a condition after the value of the IICSTIF flag is 0.
Note 5. Do not write 0 to this bit while it is 1. Generation of a condition is suspended by writing 0 to this bit while it is 1.
SIMR3 is used to control the simple I
levels.
IICSTAREQ Bit (Start Condition Generation)
When a start condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b as well as setting the
IICSTAREQ bit to 1.
[Setting condition]
 Writing 1 to the bit
[Clearing condition]
 Completion of generation of the start condition
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
IICSTIF IICSTP
IICSDAS[1:0]
REQ
0 0 0 0
Bit Name
Start Condition Generation
Stop Condition Generation
Issuing of Start, Restart, or Stop
Condition Completed Flag
SSDA Output Select
SSCL Output Select
2
C mode start and stop conditions, and to hold the SSDAn and SSCLn pins at fixed
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
IICRST IICSTA
AREQ REQ
0 0
Description
0: A start condition is not generated.
1: A start condition is generated.*
0: A restart condition is not generated.
1: A restart condition is generated.*
0: A stop condition is not generated.
1: A stop condition is generated.*
0: There are no requests for generating conditions or a
condition is being generated.
1: A start, restart, or stop condition is completely generated.
b5 b4
0 0: Serial data output
0 1: Generate a start, restart, or stop condition.
1 0: Output the low level on the SSDAn pin.
1 1: Place the SSDAn pin in the high-impedance state.
b7 b6
0 0: Serial clock output
0 1: Generate a start, restart, or stop condition.
1 0: Output the low level on the SSCLn pin.
1 1: Place the SSCLn pin in the high-impedance state.
1, 3, 4, 5
* * *
2, 3, 4, 5
* * *
2, 3, 4, 5
* * *
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