Sequence Transfer - Renesas RX100 Series User Manual

RX13T Group
Transfer information allocated in
the on-chip memory space
First data transfer
Transfer information
Second data transfer
Transfer information
Figure 16.25 Chain Transfer When the Counter is 0
16.6.3

Sequence Transfer

The following is an example of using the SCI receive interrupt as a request source of sequence transfer.
(1) Transfer Information Settings
Set the MRA.MD[1:0] bits to 00b (normal transfer mode), the MRA.SZ[1:0] bits to 00b (byte transfer), and the
MRA.SM[1:0] bits to 00b (source address is fixed). Set the MRB.CHNE bit to 0 (chain transfer is disabled), the
MRB.DISEL bit to 0 (an interrupt request to the CPU is generated on completion of the specified number of data
transfers), the MRB.DM[1:0] bits to 10b (DAR is incremented after data transfer), the MRB.INDX bit to 1 (start
sequence transfer), and the MRB.SQEND bit to 0 (continue the sequence transfer). The MRB.DTS bit can be set to any
value. Set the address of the SCIk.RDR register in the SAR register and set the start address of the RAM area which
stores the data in the DAR register.
When the MRA.WBDIS bit is set to 1 (Does not write back the transfer information), the values of registers CRA and
CRB are ignored.
(2) DTC Vector Table Setting
Set the start address of the transfer information for the corresponding receive data full interrupt (RXI) in the DTC vector
table.
(3) DTC Index Table Setting
Set the start address of the transfer information for each sequence in the DTC index table.
(4) ICU Setting and DTC Module Activation
Set the corresponding ICU.DTCERn.DTCE bit to 1 and the ICU.IERm.IENj bit to 1. Set the DTCST.DTCST bit to 1.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Chain transfer
(counter = 0)
Upper 8 bits of DAR
16. Data Transfer Controller (DTCb)
Input circuit
Input buffer
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