Timer Compare Match Clear Register (Tcntcmpclr) - Renesas RX100 Series User Manual

RX13T Group
19.2.7

Timer Compare Match Clear Register (TCNTCMPCLR)

Address(es): MTU5.TCNTCMPCLR 0009 54B6h
b7 b6
— —
Value after reset: 0 0
Bit Symbol
b0 CMPCLR5W
b1 CMPCLR5V
b2 CMPCLR5U
b7 to b3 —
TCNTCMPCLR specifies requests to clear MTU5.TCNTU, MTU5.TCNTV, and MTU5.TCNTW. The MTU has one
TCNTCMPCLR (on MTU5).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
CMPCL CMPCL
— — —
R5U
0 0 0 0
Bit Name
TCNT Compare Clear 5W
TCNT Compare Clear 5V
TCNT Compare Clear 5U
Reserved
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
CMPCL
R5V R5W
0 0
Description
0: Disables MTU5.TCNTW to be cleared to 0000h at
MTU5.TCNTW and MTU5.TGRW compare match or input
capture
1: Enables MTU5.TCNTW to be cleared to 0000h at
MTU5.TCNTW and MTU5.TGRW compare match or input
capture
0: Disables MTU5.TCNTV to be cleared to 0000h at
MTU5.TCNTV and MTU5.TGRV compare match or input
capture
1: Enables MTU5.TCNTV to be cleared to 0000h at
MTU5.TCNTV and MTU5.TGRV compare match or input
capture
0: Disables MTU5.TCNTU to be cleared to 0000h at
MTU5.TCNTU and MTU5.TGRU compare match or input
capture
1: Enables MTU5.TCNTU to be cleared to 0000h at
MTU5.TCNTU and MTU5.TGRU compare match or input
capture
These bits are read as 0. The write value should be 0.
R/W
R/W
R/W
R/W
R/W
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