Overflow In Reset-Synchronized Pwm Mode - Renesas RX100 Series User Manual

RX13T Group
19.6.16

Overflow in Reset-Synchronized PWM Mode

After reset-synchronized PWM mode is selected, MTU3.TCNT and MTU4.TCNT start counting when the CST3 bit of
TSTRA is set to 1. In this state, the MTU4.TCNT count clock source and count edge are determined by the MTU3.TCR
setting.
In reset-synchronized PWM mode, with period register MTU3.TGRA set to FFFFh and the MTU3.TGRA compare
match selected as the counter clearing source, MTU3.TCNT and MTU4.TCNT count up to FFFFh, then a compare
match occurs with MTU3.TGRA, and MTU3.TCNT and MTU4.TCNT are both cleared. In this case, a TCIVn interrupt
(n = 3, 4) is not generated.
Figure 19.135 shows an example of operation in reset-synchronized PWM mode with period register MTU3.TGRA set
to FFFFh and the MTU3.TGRA compare match specified for the counter clearing source.
MTU3.TGRA
(FFFFh)
TCIV3 interrupt signal
TCIV4 interrupt signal
Figure 19.135 Overflow in Reset-Synchronized PWM Mode
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
MTU3.TCNT =
MTU4.TCNT
0000h
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Counter cleared by MTU3.TGRA compare match
Not set
Not set
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