Output Level Control/Status Register 1 (Ocsr1) - Renesas RX100 Series User Manual

RX13T Group
20.2.5

Output Level Control/Status Register 1 (OCSR1)

Address(es): POE.OCSR1 0008 C4C2h
b15 b14
OSF1 —
Value after reset: 0 0
Bit Symbol
b7 to b0 —
b8 OIE1
b9 OCE1
b14 to b10 —
b15 OSF1
Note 1. Can be modified only once after a reset.
Note 2. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
The OCSR1 register controls the enable/disable of output-level comparison and interrupts, and indicates status.
OIE1 Bit (Simultaneous Conduction Interrupt Enable 1)
This bit enables or disables interrupt requests when the OSF1 flag is set to 1.
OCE1 Bit (Simultaneous Conduction High-Impedance Enable 1)
This bit specifies whether to put the output of the target pin in the high-impedance state when the OSF1 flag is set to 1.
OSF1 Flag (Simultaneous Conduction Flag 1)
This flag indicates that at least one of the three pairs of two-phase output pins for MTU complementary PWM output
(MTU3 and MTU4) has simultaneously become at the active level. If the high-impedance control for the corresponding
pins is not enabled, this flag does not become 1.
For setting the active level, refer to section 20.2.6, Active Level Setting Register 1 (ALR1) .
[Setting condition]
 When the MTIOC3B and MTIOC3D pins simultaneously go to the active level *
while the POECR2.MTU3BDZE bit is 1.
 When the MTIOC4A and MTIOC4C pins simultaneously go to the active level *
while the POECR2.MTU4ACZE bit is 1.
 When the MTIOC4B and MTIOC4D pins simultaneously go to the active level *
while the POECR2.MTU4BDZE bit is 1.
Note 1. The setting condition is judged only by the level of the pin regardless the setting of the MPC.PmnPFS register.
[Clearing condition]
 By writing 0 to the OSF1 flag after reading OSF1 = 1
To write 0 to this flag, the inactive level needs to be output from MTU complementary PWM output pins. For details,
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — —
0 0 0 0
Bit Name
Reserved
Simultaneous Conduction
Interrupt Enable 1
Simultaneous Conduction High-
Impedance Enable 1
Reserved
Simultaneous Conduction Flag
1
b9 b8 b7 b6
OCE1 OIE1 — —
0 0 0 0
Description
These bits are read as 0. The write value should be 0.
0: Interrupt requests disabled
1: Interrupt requests enabled
0: Does not put the outputs in the high-impedance state when
they simultaneously go to an active level.
1: Put the outputs in the high-impedance state when they
simultaneously go to an active level.
These bits are read as 0. The write value should be 0.
0: Indicates that outputs have not simultaneously become an
active level.
1: Indicates that outputs have simultaneously become an active
level.
20. Port Output Enable 3 (POE3C)
b5 b4 b3 b2
— — — —
0 0 0 0
1
for at least one cycle of PCLK
1
for at least one cycle of PCLK
1
for at least one cycle of PCLK
Page 534 of 1041
b1 b0
— —
0 0
R/W
R/W
R/W
R/W* 1
R/W
R/(W)
2
*