Receiving A Start Frame - Renesas RX100 Series User Manual

RX13T Group
23.10.3

Receiving a Start Frame

The extended serial mode control section is capable of receiving Start Frames with the structures listed in Table 23.30 .
Table 23.30 Structures of Start Frames
Bit Setting
BFE CF0RE
0 0
0 1
1 0
1 1
Figure 23.63 shows an example of operations to receive a Start Frame, which is composed of the Break Field low width,
Control Field 0, and Control Field 1. Figure 23.64 and Figure 23.65 are flowcharts for the reception of a Start Frame,
and Figure 23.66 is a state transition diagram when receiving a Start Frame.
Operations when the extended serial mode control section is to be used to receive a Start Frame are as listed below. Be
sure to use the SCI12 in asynchronous mode.
(1) With Break Field low width detection mode as the operating mode for the timer, writing 1 to the CR3.SDST bit
enables detection of the Break Field low width.
(2) Low-level input on the RXDX12 pin continuing over a period longer than that corresponding to the settings of
registers TCNT and TPRE is detected as the Break Field low width. At this time, the STR.BFDF flag is set to 1. An
SCIX0 interrupt is also generated if the value of the ICR.BFDIE bit is 1.
(3) When the input from the RXDX12 pin goes high after the Break Field low width, the CR0.RXDSF flag becomes 0
and reception of Control Field 0 starts.
(4) If the data received in Control Field 0 match the data set in the CF0DR register, the STR.CF0MF flag is set to 1. An
SCIX1 interrupt is also generated if the value of the ICR.CF0MIE bit is 1. Reception of Control Field 1 starts after
that. If the data received in Control Field 0 do not match the data set in the CF0DR register, a transition to the state
prior to Break Field low width detection proceeds.
(5) If the data received in Control Field 1 match the data set in registers PCF1DR and SCF1DR, the STR.CF1MF flag is
set to 1. An SCIX1 interrupt is also generated if the value of the ICR.CF1MIE bit is 1. Transfer of the Information
Frame starts after that. If the data received in Control Field 1 do not match the data set in either or both of registers
PCF1DR and SCF1DR, a transition to the state prior to Break Field low width detection proceeds.
Omit the Break Field and Control Field 0 to suit the structure of the Start Frame.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Control Field 0
Break Field Control Field 0
low width
23. Serial Communications Interface (SCIg, SCIh)
Structures of Start Frames
8 bits
Break Field
low width
8 bits
Information Frame
Control Field 1
8 bits
Control Field 1 Information Frame
8 bits
Information Frame
Control Field 1
8 bits
Information Frame
Control Field 1
8 bits
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