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Renesas RX Series User Manual

Renesas RX Series User Manual

32-bit mcu

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RX23W Group

32

RENESAS 32-Bit MCU

RX Family ⁄ RX200 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.00

Jul 2019

Table of Contents

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Summary of Contents for Renesas RX Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
Page 3 Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 4 Notes on Printed Circuit Board Patterns RX Family R01AN1411EJ Hardware Design Guide Examples of register initial setting — — Examples of applications and sample programs — — Renesas Technical Preliminary report on the specifications of a product, — — Update document, etc.
Page 5 2. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. X.X.X ...
Page 6 3. List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communications Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input/Output IrDA Infrared Data Association...
Page 7: Table Of Contents
Contents Features ..............................51 Overview ............................52 Outline of Specifications ........................52 List of Products ............................ 57 Block Diagram ............................. 58 Pin Functions ............................59 Pin Assignments ..........................63 CPU ............................... 69 Features ..............................69 Register Set of the CPU ........................70 2.2.1 General-Purpose Registers (R0 to R15) ..................
Page 8 2.6.1 Exception Vector Table ......................88 2.6.2 Interrupt Vector Table ........................ 89 Operation of Instructions ........................90 2.7.1 Restrictions on RMPA and String-Manipulation Instructions ........... 90 2.7.1.1 Transfer Size and Data Prefetching ................... 90 2.7.1.2 Access to the External Space ..................... 90 2.7.1.3 Access to I/O Registers .....................
Page 9 6.3.8 Determination of Reset Generation Source ................147 Option-Setting Memory (OFSM) ....................148 Overview ............................148 Register Descriptions ......................... 149 7.2.1 Option Function Select Register 0 (OFS0) ................149 7.2.2 Option Function Select Register 1 (OFS1) ................153 7.2.3 Endian Select Register (MDE) ....................154 Usage Note ............................
Page 10 9.2.15 Oscillation Stop Detection Status Register (OSTDSR) ............188 9.2.16 Main Clock Oscillator Wait Control Register (MOSCWTCR) ..........189 9.2.17 CLKOUT Output Control Register (CKOCR) ................. 190 9.2.18 Main Clock Oscillator Forced Oscillation Control Register (MOFCR) ........191 9.2.19 Memory Wait Cycle Setting Register (MEMWAIT) ............... 192 9.2.20 Low-Speed On-Chip Oscillator Trimming Register (LOCOTRR) ..........
Page 11 Clock Frequency Accuracy Measurement Circuit (CAC) ............. 210 10.1 Overview ............................210 10.2 Register Descriptions ......................... 212 10.2.1 CAC Control Register 0 (CACR0) ................... 212 10.2.2 CAC Control Register 1 (CACR1) ................... 213 10.2.3 CAC Control Register 2 (CACR2) ................... 214 10.2.4 CAC Interrupt Request Enable Register (CAICR) ..............
Page 12 11.6.3.1 Entry to Software Standby Mode ..................245 11.6.3.2 Exit from Software Standby Mode .................. 246 11.6.3.3 Example of Software Standby Mode Application ............247 11.7 Usage Notes ............................248 11.7.1 I/O Port States ........................... 248 11.7.2 Module Stop State of DMAC and DTC ................... 248 11.7.3 On-Chip Peripheral Module Interrupts ..................
Page 13 14.5.3 Access Exceptions ........................265 14.5.4 Floating-Point Exception ......................265 14.5.5 Reset ............................265 14.5.6 Non-Maskable Interrupt ......................266 14.5.7 Interrupt ............................ 266 14.5.8 Unconditional Trap ........................266 14.6 Return from Exception Handling Routine ..................267 14.7 Priority of Exception Events ......................267 Interrupt Controller (ICUb) ......................
Page 14 15.4.7 Digital Filter ..........................301 15.4.8 External Pin Interrupts ......................301 15.5 Non-maskable Interrupt Operation ....................302 15.6 Return from Power-Down States ....................... 303 15.6.1 Return from Sleep Mode or Deep Sleep Mode ................ 303 15.6.2 Return from Software Standby Mode ..................303 15.7 Usage Note ............................
Page 15 17.2.3 Memory-Protection Enable Register (MPEN) ................. 323 17.2.4 Background Access Control Register (MPBAC) ..............324 17.2.5 Memory-Protection Error Status-Clearing Register (MPECLR) ..........325 17.2.6 Memory-Protection Error Status Register (MPESTS) ............. 326 17.2.7 Data Memory-Protection Error Address Register (MPDEA) ........... 327 17.2.8 Region Search Address Register (MPSA) ................
Page 16 18.3.5 Operation Timing ........................368 18.3.6 DMAC Execution Cycles ......................369 18.3.7 Activating the DMAC ......................370 18.3.8 Starting DMA Transfer ......................371 18.3.9 Registers during DMA Transfer ....................371 18.3.10 Channel Priority ........................372 18.4 Ending DMA Transfer ........................373 18.4.1 Transfer End by Completion of Specified Total Number of Transfer Operations ....
Page 17 19.4.4 Repeat Transfer Mode ......................396 19.4.5 Block Transfer Mode ........................ 397 19.4.6 Chain Transfer .......................... 398 19.4.7 Operation Timing ........................399 19.4.8 Execution Cycles of the DTC ....................402 19.4.9 DTC Bus Mastership Release Timing ..................402 19.5 DTC Setting Procedure ........................403 19.6 Examples of DTC Usage ........................
Page 18 20.4.2 Setting Bit-Rotating Operation of Output Port Groups ............429 20.4.3 Linking DMA/DTC Transfer End Signal as Event ..............429 20.4.4 Clock Settings ........................... 429 20.4.5 Module Stop Function Setting ....................429 I/O Ports ............................430 21.1 Overview ............................430 21.2 I/O Port Configuration ........................
Page 19 23.2.2 Timer Mode Register (TMDR) ....................479 23.2.3 Timer I/O Control Register (TIOR) ..................481 23.2.4 Timer Interrupt Enable Register (TIER) .................. 491 23.2.5 Timer Status Register (TSR) ....................493 23.2.6 Timer Buffer Operation Transfer Mode Register (TBTM) ............494 23.2.7 Timer Input Capture Control Register (TICCR) ..............
Page 20 23.3.10 Noise Filter ..........................584 23.4 Interrupt Sources ..........................585 23.4.1 Interrupt Sources and Priorities ....................585 23.4.2 DTC/DMAC Activation ......................586 23.4.3 A/D Converter Activation ......................586 23.5 Operation Timing ..........................588 23.5.1 Input/Output Timing ......................... 588 23.5.2 Interrupt Signal Timing ......................594 23.6 Usage Notes ............................
Page 21 23.7.3 Overview of Pin Initialization Procedures and Mode Transitions in Case of Error during Operation .................... 612 23.8 Operations Linked by the ELC ......................638 23.8.1 Event Signal Output to the ELC ....................638 23.8.2 MTU Operations in Response to Receiving Event Signals from the ELC ....... 638 23.8.3 Notes on MTU by Event Signal Reception from the ELC ............
Page 22 25.2.9 Timer Synchronous Register (TSYR) ..................680 25.2.10 Noise Filter Control Register (NFCR) ..................681 25.3 Operation ............................683 25.3.1 Basic Functions ......................... 683 25.3.2 Synchronous Operation ......................689 25.3.3 Buffer Operation ........................691 25.3.4 Cascaded Operation ........................694 25.3.5 PWM Modes ..........................
Page 23 26.2.3 Time Constant Register B (TCORB) ..................732 26.2.4 Timer Control Register (TCR) ....................733 26.2.5 Timer Counter Control Register (TCCR) ................. 734 26.2.6 Timer Control/Status Register (TCSR) ..................736 26.2.7 Timer Counter Start Register (TCSTR) ..................738 26.3 Operation ............................739 26.3.1 Pulse Output ..........................
Page 24 27.2.5 Compare Match Constant Register (CMCOR) ................. 757 27.3 Operation ............................758 27.3.1 Periodic Count Operation ......................758 27.3.2 CMCNT Count Timing ......................758 27.4 Interrupts ............................759 27.4.1 Interrupt Sources ........................759 27.4.2 Timing of Compare Match Interrupt Generation ..............759 27.5 Link Operations by ELC ........................
Page 25 28.2.22 Second Capture Register n (RSECCPn) (n = 0, 1)/BCNT0 Capture Register n (BCNT0CPn) (n = 0, 1) ......................787 28.2.23 Minute Capture Register n (RMINCPn) (n = 0, 1)/BCNT1 Capture Register n (BCNT1CPn) (n = 0, 1) ......................788 28.2.24 Hour Capture Register n (RHRCPn) (n = 0, 1)/BCNT2 Capture Register n (BCNT2CPn) (n = 0, 1) ......................
Page 26 29.2.6 Low-Power Timer Standby Wakeup Enable Register (LPWUCR) ......... 815 29.3 Operation ............................816 29.3.1 Periodic Counting Operation ....................816 29.3.2 Count Timing of Low-Power Timer Counter ................818 29.3.3 Clearing Timing of Low-Power Timer Counter ............... 818 29.4 Wakeup from Software Standby Mode by an Interrupt through the Event Link Controller (ELC) .. 819 29.5 Usage Notes ............................
Page 27 31.3.4 Status Flags ..........................850 31.3.5 Reset Output ..........................850 31.3.6 Interrupt Sources ........................850 31.3.7 Reading the Counter Value ....................... 851 31.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers ... 852 31.4 Link Operation by ELC ........................852 31.5 Usage Notes ............................
Page 28 32.2.26 Pipe Window Select Register (PIPESEL) ................893 32.2.27 Pipe Configuration Register (PIPECFG) .................. 894 32.2.28 Pipe Maximum Packet Size Register (PIPEMAXP) ..............896 32.2.29 Pipe Cycle Control Register (PIPEPERI) ................. 897 32.2.30 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) ..............898 32.2.31 PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 1 to 5) ........
Page 29 32.3.4.7 Data PID Sequence Bit ....................938 32.3.4.8 Response PID = NAK Function ..................938 32.3.4.9 Auto Response Mode ...................... 938 32.3.4.10 OUT-NAK Mode ......................938 32.3.4.11 Null Auto Response Mode ....................939 32.3.5 FIFO Buffer Memory ....................... 939 32.3.5.1 FIFO Buffer Memory ......................
Page 30 33.2.9 Serial Status Register (SSR) ..................... 981 33.2.10 Smart Card Mode Register (SCMR) ..................986 33.2.11 Bit Rate Register (BRR) ......................988 33.2.12 Modulation Duty Register (MDDR) ..................996 33.2.13 Serial Extended Mode Register (SEMR) .................. 997 33.2.14 Noise Filter Setting Register (SNFR) ..................1000 33.2.15 C Mode Register 1 (SIMR1) ....................
Page 31 33.4.1 Multi-Processor Serial Data Transmission ................1034 33.4.2 Multi-Processor Serial Data Reception .................. 1035 33.5 Operation in Clock Synchronous Mode ..................1038 33.5.1 Clock ............................1038 33.5.2 CTS and RTS Functions ......................1039 33.5.3 SCI Initialization (Clock Synchronous Mode) ............... 1040 33.5.4 Serial Data Transmission (Clock Synchronous Mode) ............
Page 32 33.10.6 Bit Rate Measurement ......................1088 33.10.7 Selectable Timing for Sampling Data Received through RXDX12 ........1089 33.10.8 Timer ............................1090 33.11 Noise Cancellation Function ......................1092 33.12 Interrupt Sources ..........................1093 33.12.1 Buffer Operations for TXI and RXI Interrupts ............... 1093 33.12.2 Interrupts in Asynchronous Mode, Clock Synchronous Mode, and Simple SPI Mode ..
Page 33 C-bus Interface (RIICa) ......................1113 35.1 Overview ............................1113 35.2 Register Descriptions ........................1116 35.2.1 C-bus Control Register 1 (ICCR1) ..................1116 35.2.2 C-bus Control Register 2 (ICCR2) ..................1118 35.2.3 C-bus Mode Register 1 (ICMR1) ..................1122 35.2.4 C-bus Mode Register 2 (ICMR2) ..................1123 35.2.5 C-bus Mode Register 3 (ICMR3) ..................
Page 34 35.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) ....1176 35.9.3 Slave Arbitration-Lost Detection (SALE Bit) ................ 1177 35.10 Start Condition/Restart Condition/Stop Condition Issuing Function ..........1178 35.10.1 Issuing a Start Condition ......................1178 35.10.2 Issuing a Restart Condition ..................... 1178 35.10.3 Issuing a Stop Condition ......................
Page 35 36.2.17 Receive Rule Number Configuration Register (GAFLCFG) ..........1210 36.2.18 Receive Rule Entry Register jAL (GAFLIDLj) (j = 0 to 15) ..........1211 36.2.19 Receive Rule Entry Register jAH (GAFLIDHj) (j = 0 to 15) ..........1212 36.2.20 Receive Rule Entry Register jBL (GAFLMLj) (j = 0 to 15) ..........1213 36.2.21 Receive Rule Entry Register jBH (GAFLMHj) (j = 0 to 15) ..........
Page 36 36.2.58 Transmit/Receive FIFO Message Lost Status Register (CFMSTS) ........1243 36.2.59 Receive FIFO Interrupt Status Register (RFISTS) ..............1244 36.2.60 Transmit/Receive FIFO Receive Interrupt Status Register (CFISTS) ........1244 36.2.61 Transmit Buffer Control Register p (TMCp) (p = 0 to 3) ............1245 36.2.62 Transmit Buffer Status Register p (TMSTSp) (p = 0 to 3) .............
Page 37 36.7 Interrupt ............................1278 36.8 RAM Window ..........................1281 36.9 Initial Settings ..........................1282 36.9.1 Clock Setting .......................... 1283 36.9.2 Bit Timing Setting ........................1283 36.9.3 Communication Speed Setting ....................1284 36.9.4 Receive Rule Setting ......................1285 36.9.5 Buffer Setting ......................... 1286 36.10 Reception Procedure ........................
Page 38 37.5.2 Notes on Changing Transmission Modes ................1330 37.5.3 Limits on WS Continue Mode ....................1330 Serial Peripheral Interface (RSPIa) .................... 1331 38.1 Overview ............................1331 38.2 Register Descriptions ........................1335 38.2.1 RSPI Control Register (SPCR) ....................1335 38.2.2 RSPI Slave Select Polarity Register (SSLP) ................1337 38.2.3 RSPI Pin Control Register (SPPCR) ..................
Page 39 38.3.7 Transmit Buffer Empty/Receive Buffer Full Interrupts ............1379 38.3.8 Error Detection ........................1381 38.3.8.1 Overrun Error ........................ 1382 38.3.8.2 Parity Error ........................1384 38.3.8.3 Mode Fault Error ......................1385 38.3.9 Initializing RSPI ........................1386 38.3.9.1 Initialization by Clearing the SPE Bit ................1386 38.3.9.2 System Reset .........................
Page 40 40.2.1 Command Register (SDCMD) ....................1421 40.2.2 Argument Register (SDARG) ....................1423 40.2.3 Data Stop Register (SDSTOP) ....................1423 40.2.4 Block Count Register (SDBLKCNT) ..................1424 40.2.5 Response Register 10 (SDRSP10), Response Register 32 (SDRSP32), Response Register 54 (SDRSP54), Response Register 76 (SDRSP76) ......... 1425 40.2.6 SD Status Register 1 (SDSTS1) .....................
Page 41 40.3.6.9 IO_RW_EXTENDED (CMD53 Multi-Block Write) ........... 1465 40.3.6.10 DMA Transfer ....................... 1467 40.4 Interrupts ............................1469 40.4.1 DMA Transfer Triggered by Interrupt Requests ..............1470 40.5 Notes on Using the SDHI ........................ 1471 40.5.1 Illegal Read Access During a Multi-Block Read and How To Avoid It ........ 1471 40.5.2 SDBUFR Register Illegal Write Error ..................
Page 42 43.2.4 CTSU Sensor Stabilization Wait Control Register (CTSUSST) ..........1496 43.2.5 CTSU Measurement Channel Register 0 (CTSUMCH0) ............1497 43.2.6 CTSU Measurement Channel Register 1 (CTSUMCH1) ............1498 43.2.7 CTSU Channel Enable Control Register n (CTSUCHACn) (n = 0 to 3) ....... 1499 43.2.8 CTSU Channel Enable Control Register 4 (CTSUCHAC4) ..........
Page 43 44.2.4 A/D Channel Select Register A0 (ADANSA0) ..............1541 44.2.5 A/D Channel Select Register A1 (ADANSA1) ..............1542 44.2.6 A/D Channel Select Register B0 (ADANSB0) ..............1543 44.2.7 A/D Channel Select Register B1 (ADANSB1) ..............1544 44.2.8 A/D-Converted Value Addition/Average Function Select Register 0 (ADADS0) ....1545 44.2.9 A/D-Converted Value Addition/Average Function Select Register 1 (ADADS1) ....
Page 44 44.3.2 Single Scan Mode ........................1585 44.3.2.1 Basic Operation ......................1585 44.3.2.2 Channel Selection and Self-Diagnosis ................1586 44.3.2.3 A/D Conversion of Temperature Sensor Output/Internal Reference Voltage ....1587 44.3.2.4 A/D Conversion in Double Trigger Mode ..............1588 44.3.3 Continuous Scan Mode ......................1589 44.3.3.1 Basic Operation ......................
Page 45 44.8.10 ADHSC Bit Rewriting Procedure ................... 1617 44.8.11 Voltage Range of Analog Power Supply Pins ................ 1618 44.8.12 Notes on Board Design ......................1619 44.8.13 Notes on Noise Prevention ..................... 1619 12-Bit D/A Converter (R12DAA) ....................1620 45.1 Overview ............................1620 45.2 Register Descriptions ........................
Page 46 47.3 Operation ............................1644 47.3.1 Comparator Bn Digital Filter (n = 2, 3) .................. 1648 47.3.2 Comparator Bn Output Function (n = 2, 3) ................1649 47.3.3 Example of Using Comparator B to Exit Software Standby Mode ........1649 47.4 Comparator B2 and Comparator B3 Interrupts ................
Page 47 50.4.10 Flash Extra Area Control Register (FEXCR) ................. 1671 50.4.11 Flash Processing Start Address Register H (FSARH) ............1672 50.4.12 Flash Processing Start Address Register L (FSARL) ............. 1672 50.4.13 Flash Processing End Address Register H (FEARH) ............. 1673 50.4.14 Flash Processing End Address Register L (FEARL) ..............
Page 48 50.8.3.1 Operating Conditions in Boot Mode (FINE Interface) ..........1706 50.9 Flash Memory Protection ........................ 1707 50.9.1 ID Code Protection ......................... 1707 50.9.1.1 Boot Mode ID Code Protection ..................1708 50.9.1.2 On-Chip Debugging Emulator ID Code Protection ............1709 50.9.2 ROM Code Protection ......................
Page 49 50.11.4 Procedure for Transition to the Program/Erase Host Command Wait State ......1734 50.11.5 Procedure to Unlock Boot Mode ID Code Protection ............1735 50.11.6 Procedure to Erase the User Area and Data Area ..............1736 50.11.7 Procedure to Program the User Area and Data Area .............. 1737 50.11.8 Procedure to Check Data in the User Area ................
Page 50 51.16.1 Connecting VCL Capacitor and Bypass Capacitors ............... 1816 Appendix 1. Port States in Each Processing Mode ................1817 Appendix 2. Package Dimensions ....................... 1818 REVISION HISTORY ........................... 1820...
Page 51: Features
RX23W Group R01UH0823EJ0100 Rev.1.00 Renesas MCUs Jul 31, 2019 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory,  5.0, various communication functions including USB 2.0 full-speed host/function/OTG, CAN, Bluetooth SD host interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D converter,...
Page 52: Overview
RX23W Group 1. Overview Overview Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type.
Page 53 RX23W Group 1. Overview Table 1.1 Outline of Specifications (2/4) Classification Module/Function Description Low power Low power consumption  Module stop function  Three low power consumption modes consumption functions Sleep mode, deep sleep mode, and software standby mode  Low power timer that operates during the software standby state Function for lower operating ...
Page 54 RX23W Group 1. Overview Table 1.1 Outline of Specifications (3/4) Classification Module/Function Description Independent watchdog  14 bits × 1 channel Timers  Count clock: Dedicated low-speed on-chip oscillator for the IWDT timer (IWDTa) Frequency divided by 1, 16, 32, 64, 128, or 256 Realtime clock (RTCe) ...
Page 55 RX23W Group 1. Overview Table 1.1 Outline of Specifications (4/4) Classification Module/Function Description Communication Serial Sound Interface (SSI)  1 channel  Capable of duplex communications functions  Various serial audio formats supported  Master/slave function supported  Programmable word clock or bit clock generation function ...
Page 56 RX23W Group 1. Overview Table 1.2 Comparison of Functions for Different Packages RX23W Group Module/Functions 85 Pins 56 Pins External bus External bus Not supported Interrupts External interrupts NMI, IRQ0, IRQ1, IRQ4 to IRQ7 DMA controller 4 channels (DMAC0 to DMAC3) Data transfer controller Available Timers...
Page 57: List Of Products
7: 384 Kbyte/64 Kbytes/8 Kbytes Group name 3W: RX23W Group Series name RX200 Series Type of memory F: Flash memory version Renesas MCU Renesas semiconductor product Figure 1.1 How to Read the Product Part Number R01UH0823EJ0100 Rev.1.00 Page 57 of 1823 Jul 31, 2019...
Page 58: Block Diagram
RX23W Group 1. Overview Block Diagram Figure 1.2 shows a block diagram. E2 DataFlash SDHIa WDTA RSCAN IWDTa CTSU SCIg × 3 channels (including IrDA × 1 channel) SCIh × 1 channel RSPIa × 1 channel RIICa × 1 channel USB 2.0 host/function module TPUa ×...
Page 59: Pin Functions
RX23W Group 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/4) Classifications Pin Name Description Power supply Input Power supply pin. Connect it to the system power supply. — Connect this pin to the VSS pin via a 4.7 μF smoothing capacitor used to stabilize the internal power supply.
Page 60 RX23W Group 1. Overview Table 1.4 Pin Functions (2/4) Classifications Pin Name Description Port output POE0#, POE1#, POE3#, Input Input pins for request signals to place the MTU pins in the high impedance enable 2 POE8# state. Realtime clock RTCOUT Output Output pin for the 1-Hz/64-Hz clock.
Page 61 RX23W Group 1. Overview Table 1.4 Pin Functions (3/4) Classifications Pin Name Description Serial peripheral RSPCKA Input/output pin for the RSPI clock. interface MOSIA Input/output pin for transmitting data from the RSPI master. MISOA Input/output pin for transmitting data from the RSPI slave. SSLA0 Input/output pin to select the slave for the RSPI.
Page 62 RX23W Group 1. Overview Table 1.4 Pin Functions (4/4) Classifications Pin Name Description I/O ports P03, P05, P07 3-bit input/output pins. P14 to P17 4-bit input/output pins. P21, P22, P25 to P27 5-bit input/output pins. P30, P31, P35 to P37 5-bit input/output pins (P35 input pin).
Page 63: Pin Assignments
RX23W Group 1. Overview Pin Assignments Figure 1.3 and Figure 1.4 show the pin assignments. Table 1.5 and Table 1.6 show the lists of pins and pin functions. RX23W Group PTBG0085KB-A (85-pin BGA) (Upper perspective view) VSS_ DCLO AVCC XTAL XTAL VSS_ VSS_...
Page 64 RX23W Group 1. Overview VSS_RF VCC_RF DCLIN_D DCLIN_A RX23W Group P47/CLKOUT_RF PVQN0056LA-A VSS_USB (56-pin QFN) USB0_DP USB0_DM (Top view) VREFL0 VCC_USB VREFH0 AVCC0 AVSS0 Note: VSS_RF is assigned as the exposed die pad. For details, refer to Appendix 2, Package Dimensions. Figure 1.4 Pin Assignments of the 56-Pin QFN R01UH0823EJ0100 Rev.1.00...
Page 65 RX23W Group 1. Overview Table 1.5 List of Pins and Pin Functions (85-Pin BGA) (1/2) Power Supply, Timers Communications Memory Clock, System (MTU, TPU, TMR, RTC, CMT, (SCI, RSPI, RIIC, RSCAN, USB, Interface Touch Control I/O Port POE, CAC) SSI) (SDHI) sensing Others...
Page 66 RX23W Group 1. Overview Table 1.5 List of Pins and Pin Functions (85-Pin BGA) (2/2) Power Supply, Timers Communications Memory Clock, System (MTU, TPU, TMR, RTC, CMT, (SCI, RSPI, RIIC, RSCAN, USB, Interface Touch Control I/O Port POE, CAC) SSI) (SDHI) sensing Others...
Page 67 RX23W Group 1. Overview Table 1.6 List of Pins and Pin Functions (56-PinQFN) (1/2) Power Supply, Timers Clock, System (MTU, TPU, TMR, RTC, CMT, POE, Communications Touch Control I/O Port CAC) (SCI, RSPI, RIIC, RSCAN, USB, SSI) sensing Others FINED XCIN XCOUT RES#...
Page 68 RX23W Group 1. Overview Table 1.6 List of Pins and Pin Functions (56-PinQFN) (2/2) Power Supply, Timers Clock, System (MTU, TPU, TMR, RTC, CMT, POE, Communications Touch Control I/O Port CAC) (SCI, RSPI, RIIC, RSCAN, USB, SSI) sensing Others AN006 AN005 AN001 VREFL0...
Page 69: Cpu
RX23W Group 2. CPU The RXv2 instruction set architecture (RXv2) has upward compatibility with the RXv1 instruction set architecture (RXv1).  Adoption of variable-length instruction format As with RXv1, the RXv2 CPU has short formats for frequently used instructions, facilitating the development of efficient programs that take up less memory.
Page 70: Register Set Of The Cpu
RX23W Group 2. CPU Register Set of the CPU The RXv2 CPU has sixteen general-purpose registers, ten control registers, and two accumulator used for DSP instructions. Control register General-purpose register R0 (SP) ISP (Interrupt stack pointer) USP (User stack pointer) INTB (Interrupt table register) PC (Program counter) PSW (Processor status word)
Page 71: General-Purpose Registers (R0 To R15)
RX23W Group 2. CPU 2.2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen 32-bit general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 72: Interrupt Stack Pointer (Isp)/User Stack Pointer (Usp)
RX23W Group 2. CPU 2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) Value after reset: Value after reset: The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 73: Processor Status Word (Psw)
RX23W Group 2. CPU 2.2.2.5 Processor Status Word (PSW) — — — — IPL[3:0] — — — — — Value after reset: — — — — — — — — — — — — Value after reset: Symbol Bit Name Description Carry Flag 0: No carry has occurred.
Page 74: Backup Pc (Bpc)
RX23W Group 2. CPU C Flag (Carry Flag) This flag retains the state of the bit after a carry, borrow, or shift-out has occurred. Z Flag (Zero Flag) This flag is set to 1 if the result of an operation is 0; otherwise its value is cleared to 0. S Flag (Sign Flag) This flag is set to 1 if the result of an operation is negative;...
Page 75: Backup Psw (Bpsw)
RX23W Group 2. CPU 2.2.2.7 Backup PSW (BPSW) Undefined Value after reset: The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW.
Page 76: Floating-Point Status Word (Fpsw)
RX23W Group 2. CPU 2.2.2.9 Floating-Point Status Word (FPSW) — — — — — — — — — — Value after reset: — — RM[1:0] Value after reset: Symbol Bit Name Description b1, b0 RM[1:0] Floating-Point Rounding-Mode b1 b0 0 0: Rounding towards the nearest value Setting 0 1: Rounding towards 0 1 0: Rounding towards + ...
Page 77 RX23W Group 2. CPU Symbol Bit Name Description Floating-Point Error Summary Flag This bit reflects the logical OR of the FU, FZ, FO, and FV flags. Note 1. Writing 0 to the bit clears it. Writing 1 to the bit does not affect its value. Note 2.
Page 78: Accumulator
RX23W Group 2. CPU operation instruction, the bit decides whether the CPU will start handling the exception. When the bit is set to 0, the exception handling is masked; when the bit is set to 1, the exception handling is enabled. FV Flag (Invalid Operation Flag), FO Flag (Overflow Flag), FZ Flag (Division-by-Zero Flag), FU Flag (Underflow Flag), and FX Flag (Inexact Flag) While the exception handling enable bit (Ej) is 0 (exception handling is masked), if any of five floating-point exceptions...
Page 79: Processor Mode
RX23W Group 2. CPU Processor Mode The RXv2 CPU supports two processor modes, supervisor and user. These processor modes and the memory protection function enable the realization of a hierarchical CPU resource protection and memory protection mechanism. Each processor mode imposes a level on rights of access to memory and the instructions that can be executed. Supervisor mode carries greater rights than user mode.
Page 80: Data Types
RX23W Group 2. CPU Data Types The RXv2 CPU can handle four types of data: integer, floating-point, bit, and string. For details, refer to RX Family RXv2 Instruction Set Architecture User's Manual: Software. 2.4.1 Integer An integer can be signed or unsigned. For signed integers, negative values are represented by two's complements. Signed byte (8-bit) integer Unsigned byte (8-bit) integer Signed word (16-bit) integer...
Page 81: Floating-Points
RX23W Group 2. CPU 2.4.2 Floating-Points Floating-point support is for the single-precision floating-point type specified in the IEEE754 standard; operands of this type can be used in eleven floating-point operation instructions: FADD, FCMP, FDIV, FMUL, FSQRT, FSUB, FTOI, FTOU, ITOF, ROUND, and UTOF. Single-precision floating-point S: Sign (1 bit) E: Exponent (8 bits)
Page 82: Strings
RX23W Group 2. CPU 2.4.4 Strings The string data type consists of an arbitrary number of consecutive byte (8-bit), word (16-bit), or longword (32-bit) units. Seven string manipulation instructions are provided for use with strings: SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, and SWHILE.
Page 83: Endian
RX23W Group 2. CPU Endian For the RXv2 CPU, instructions are little endian, but the treatment of data is selectable as little or big endian. 2.5.1 Switching the Endian As arrangements of bytes, this MCU supports both big endian, where the higher-order byte (MSB) is at location 0, and little endian, where the lower-order byte (LSB) is at location 0.
Page 84 RX23W Group 2. CPU Table 2.3 32-Bit Write Operations when Little Endian has been Selected Operation Address Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit of dest to address 0 to address 1 to address 2 to address 3...
Page 85 RX23W Group 2. CPU Table 2.6 16-Bit Read Operations when Big Endian has been Selected Operation Reading Reading Reading Reading Reading Reading Reading Address a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from...
Page 86: Access To I/O Registers
RX23W Group 2. CPU Table 2.10 8-Bit Read Operations when Big Endian has been Selected Operation Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit Address of src from address 0 from address 1 from address 2 from address 3 Address 0...
Page 87: Data Arrangement
RX23W Group 2. CPU 2.5.4 Data Arrangement 2.5.4.1 Data Arrangement in Registers Figure 2.6 shows the relation between the sizes of registers and bit numbers. Byte (8-bit) data Word (16-bit) data Longword (32-bit) data Figure 2.6 Data Arrangement in Registers 2.5.4.2 Data Arrangement in Memory Data in memory have three sizes: byte (8-bit), word (16-bit), and longword (32-bit).
Page 88: Vector Table
RX23W Group 2. CPU Vector Table There are two types of vector table: exception and interrupt. Each vector in the vector table consists of four bytes and specifies the address where the corresponding exception handling routine starts. 2.6.1 Exception Vector Table In the exception vector table, the individual vectors for the privileged instruction exception, access exception, undefined instruction exception, floating-point exception, and non-maskable interrupt are allocated to the 124-byte area where the value indicated by the exception table register (EXTB) is used as the starting address (ExtBase).
Page 89: Interrupt Vector Table
RX23W Group 2. CPU 2.6.2 Interrupt Vector Table The address where the interrupt vector table is placed can be adjusted. The table is a 1,024-byte region that contains all vectors for unconditional traps and interrupts and starts at the address (IntBase) specified in the interrupt table register (INTB).
Page 90: Operation Of Instructions
RX23W Group 2. CPU Operation of Instructions 2.7.1 Restrictions on RMPA and String-Manipulation Instructions 2.7.1.1 Transfer Size and Data Prefetching The RMPA instruction and the string-manipulation instructions (SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, and SWHILE instructions) transfer data in longword units to speed up the reading of data from and writing of data to the memory.
Page 91: Number Of Cycles
RX23W Group 2. CPU Number of Cycles 2.8.1 Instruction and Number of Cycle Table 2.13 to Table 2.20 show the number of cycles in operation of each instruction. The listed numbers of cycles for access to memory are the numbers of cycles during no-wait access. The operands in the table below indicate the following meanings.
Page 92 RX23W Group 2. CPU Table 2.14 Number of Cycles for Transfer Instructions Mnemonic Instruction (indicates the common operation when the size is omitted) Number of Cycles  MOV “#IMM, Rd”/“Rs, Rd” Transfer instructions  {MOVU, REVL, REVW} “Rs, Rd” (register-register, immediate- ...
Page 93 RX23W Group 2. CPU Table 2.16 Number of Cycles for Branch Instructions Mnemonic Instruction (indicates the common operation when the size is omitted) Number of Cycles  B Cnd “pcdsp” Branch instructions Branch taken: 3  {BRA, BSR} “pcdsp”/“Rs” Branch not taken: 1 ...
Page 94 RX23W Group 2. CPU Table 2.19 Number of Cycles for String Manipulation Instructions Mnemonic Instruction (indicates the common operation when the size is omitted) Number of Cycles  SCMPU String manipulation instructions* 2+4×floor(n/4)+4×(n%4) n: Number of comparison bytes*  SMOVB n>3?6+3×floor(n/4)+3×(n%4):2+3n n: Number of transfer bytes* ...
Page 95: Numbers Of Cycles For Response To Interrupts
RX23W Group 2. CPU 2.8.2 Numbers of Cycles for Response to Interrupts Table 2.21 lists numbers of cycles taken by processing for response to interrupts. Table 2.21 Numbers of Cycles for Response to Interrupts Type of Interrupt Request/Details of Processing Fast Interrupt Other Interrupts 2 cycles...
Page 96: Operating Modes
RX23W Group 3. Operating Modes Operating Modes Operating Mode Types and Selection There are two types of operating-mode selection: one is be selected by the level on pins at the time of release from the reset state, and the other is selected by software after release from the reset state. Table 3.1 shows the relationship between levels on the mode-setting pins (MD, UB) on release from the reset state and the operating mode selected at that time.
Page 97: Register Descriptions
RX23W Group 3. Operating Modes Register Descriptions 3.2.1 Mode Monitor Register (MDMONR) Address(es): 0008 0000h — — — — — — — — — — — — — — — Value after reset: 0/1* Symbol Bit Name Description MD Pin Status Flag 0: The MD pin is low.
Page 98: System Control Register 1 (Syscr1)
RX23W Group 3. Operating Modes 3.2.2 System Control Register 1 (SYSCR1) Address(es): 0008 0008h — — — — — — — — — — — — — — — RAME Value after reset: Symbol Bit Name Description RAME RAM Enable 0: The RAM is disabled.
Page 99: Details Of Operating Modes
RX23W Group 3. Operating Modes Details of Operating Modes 3.3.1 Single-Chip Mode In this mode, all I/O ports can be used as general input/output ports, peripheral function input/output, or interrupt input pins. The chip starts up in single-chip mode if the high level is on the MD pin on release from the reset state. 3.3.2 Boot Mode In this mode, the on-chip flash memory modifying program (boot program) stored in a dedicated area within the MCU...
Page 100: Transitions Of Operating Modes
RX23W Group 3. Operating Modes Transitions of Operating Modes 3.4.1 Operating Mode Transitions Determined by the Mode-Setting Pins Figure 3.1 shows operating mode transitions determined by the settings of the MD pin and the UB pin. Reset MD = High RES# = High RES# = Low MD = Low...
Page 101: Address Space
RX23W Group 4. Address Space Address Space Address Space This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 4.1 shows the memory maps in the respective operating modes.
Page 102 RX23W Group 4. Address Space Single-chip mode 0000 0000h 0001 0000h Reserved area 0008 0000h Peripheral I/O registers 0010 0000h On-chip ROM (E2 Data Flash) 0010 2000h Reserved area 007F C000h Peripheral I/O registers 007F C500h Reserved area 007F FC00h Peripheral I/O registers 0080 0000h Reserved area...
Page 103: I/O Registers
RX23W Group 5. I/O Registers I/O Registers This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as shown below. Notes on writing to registers are also given below. (1) I/O register addresses (address order) ...
Page 104 RX23W Group 5. I/O Registers  Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] [R1].L, R1 ;; Next process If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary to read or execute operation for all the registers that were written to.
Page 105: I/O Register Addresses (Address Order)
RX23W Group 5. I/O Registers I/O Register Addresses (Address Order) Table 5.1 List of I/O Registers (Address Order) (1/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 0000h SYSTEM...
Page 106 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (2/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 2004h DMAC0 DMA Destination Address Register DMDAR 2 ICLK...
Page 107 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (3/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 6408h Region-1 Start Page Number Register RSPAGE1 1 ICLK section 17.
Page 108 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (4/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 8006h CMT0 Compare Match Constant Register CMCOR 2 or 3 PCLKB...
Page 109 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (5/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 8130h TPU2 Timer Control Register 2 or 3 PCLKB 2 ICLK...
Page 110 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (6/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 8210h TMR2 Timer Control Register 2 or 3 PCLKB 2 ICLK...
Page 111 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (7/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 838Fh RSPI0 RSPI Control Register 2 SPCR2 2 or 3 PCLKB...
Page 112 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (8/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 908Ch S12AD A/D Compare Function Window A/B Status Monitor Register ADWINMON 2 or 3 PCLKB 2 ICLK...
Page 113 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (9/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 90E7h S12AD A/D Sampling State Register 7 ADSSTR7 2 or 3 PCLKB...
Page 114 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (10/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 A100h SMCI8 Serial Mode Register 2 or 3 PCLKB 2 ICLK...
Page 115 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (11/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 AC20h SDHI Response Register 32 SDRSP32 3 or 4 PCLKB...
Page 116 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (12/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 AC68h SDHI SDIO Mode Control Register SDIOMD 3 or 4 PCLKB...
Page 117 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (13/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 B119h Event Link Setting Register 24 ELSR24 2 or 3 PCLKB 2 ICLK...
Page 118 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (14/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 B326h SCI12 Interrupt Control Register 2 or 3 PCLKB 2 ICLK...
Page 119 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (15/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 C06Eh PORTE Port Mode Register 2 or 3 PCLKB 2 ICLK...
Page 120 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (16/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 C164h P44 Pin Function Control Register P44PFS 2 or 3 PCLKB 2 ICLK...
Page 121 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (17/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 0008 C416h Binary Counter 3 Alarm Register BCNT3AR 2 or 3 PCLKB 2 ICLK...
Page 122 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (18/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 0018h USB0 D0FIFO Port Register D0FIFO 3, 4 PCLKB...
Page 123 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (19/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 0056h USB0 USB Request Value Register USBVAL 9 PCLKB...
Page 124 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (20/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 007Ch USB0 PIPE7 Control Register PIPE7CTR 9 PCLKB...
Page 125 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (21/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 00D2h USB0 Device Address 1 Configuration Register DEVADD1 9 PCLKB...
Page 126 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (22/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 8328h RSCAN Global Control Register H GCTRH 2 or 3 PCLKB...
Page 127 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (23/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 83AAh RSCAN Receive Buffer Register 0CH RMDF10 2 or 3 PCLKB...
Page 128 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (24/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 83DEh RSCAN Receive Buffer Register 3DH RMDF33 2 or 3 PCLKB...
Page 129 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (25/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 8412h RSCAN Receive Buffer Register 7AH RMIDH7 2 or 3 PCLKB...
Page 130 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (26/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 8446h RSCAN Receive Buffer Register 10BH RMPTR10 2 or 3 PCLKB...
Page 131 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (27/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 8496h RSCAN Receive Buffer Register 15BH RMPTR15 2 or 3 PCLKB...
Page 132 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (28/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 85EAh RSCAN RAM Test Register 53 RPGACC53 2 or 3 PCLKB...
Page 133 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (29/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000A 8630h RSCAN0 Transmit Buffer Register 3AL TMIDL3 2 or 3 PCLKB...
Page 134 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (30/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 000D 0A36h Timer Output Level Buffer Register TOLBR 2 or 3 PCLKA 2 ICLK...
Page 135 RX23W Group 5. I/O Registers Table 5.1 List of I/O Registers (Address Order) (31/31) Number of Access Cycles Module Register Number Access Reference ICLK  PCLK Address Symbol Register Name Symbol of Bits Size ICLK <PCLK Section 007F C0ADh TEMPSA Temperature Sensor Calibration Data Register H TSCDRH 2 or 3 PCLKA...
Page 136: Resets
RX23W Group 6. Resets 6. Resets Overview The following resets are implemented: RES# pin reset, power-on reset, voltage monitoring 0 reset, voltage monitoring 1 reset, independent watchdog timer reset, watchdog timer reset, and software reset. Table 6.1 lists the reset names and sources. Table 6.1 Reset Names and Sources Reset Name...
Page 137 RX23W Group 6. Resets The internal state and pins are initialized by a reset. Table 6.2 lists the reset targets to be initialized. Table 6.2 Targets Initialized by Each Reset Source Reset Source Voltage Independent Voltage Power-On Monitoring 0 Watchdog Watchdog Monitoring 1 Target to be Initialized...
Page 138: Register Descriptions
RX23W Group 6. Resets Register Descriptions 6.2.1 Reset Status Register 0 (RSTSR0) Address(es): 0008 C290h LVD1R LVD0R — — — — — PORF Value after reset: Symbol Bit Name Description PORF Power-On Reset Detect Flag 0: Power-on reset not detected. R(/W) 1: Power-on reset detected.
Page 139: Reset Status Register 1 (Rstsr1)
RX23W Group 6. Resets 6.2.2 Reset Status Register 1 (RSTSR1) Address(es): 0008 C291h — — — — — — — CWSF Value after reset: Symbol Bit Name Description CWSF Cold/Warm Start Determination Flag 0: Cold start R(/W) 1: Warm start b7 to b1 —...
Page 140: Reset Status Register 2 (Rstsr2)
RX23W Group 6. Resets 6.2.3 Reset Status Register 2 (RSTSR2) Address(es): 0008 00C0h SWRF WDTR IWDTR — — — — — Value after reset: Symbol Bit Name Description IWDTRF Independent Watchdog Timer Reset Detect 0: Independent watchdog timer reset not detected. R(/W) Flag 1: Independent watchdog timer reset detected.
Page 141: Software Reset Register (Swrr)
RX23W Group 6. Resets 6.2.4 Software Reset Register (SWRR) Address(es): 0008 00C2h SWRR[15:0] Value after reset: Symbol Bit Name Description b15 to b0 SWRR[15:0] Software Reset Writing A501h resets the MCU. These bits are read as 0000h. Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register. R01UH0823EJ0100 Rev.1.00 Page 141 of 1823 Jul 31, 2019...
Page 142: Operation
RX23W Group 6. Resets Operation 6.3.1 RES# Pin Reset This is a reset generated by the RES# pin. When the RES# pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to unfailingly reset the LSI, the RES# pin should be held low for the specified power supply stabilization time at a power-on.
Page 143 RX23W Group 6. Resets 4.7 k (reference value) RES# Vdet0 VPOR External voltage RES# pin Voltage monitoring 0 reset state Power-on reset state POR detection signal (Low is valid) LVD0 enable/disable Set by OFS1.LVDAS signal (Low is valid) Voltage detection 0 signal (Low is valid) tPOR tLVD...
Page 144: Voltage Monitoring 1 Reset
RX23W Group 6. Resets 6.3.3 Voltage Monitoring 1 Reset The voltage monitoring 1 reset is internal resets generated by the voltage monitoring circuit. When the voltage monitoring 1 interrupt/reset enable bit (LVD1RIE) is set to 1 (enabling generation of a reset or interrupt by the voltage detection circuit) and the voltage monitoring 1 circuit mode select bit (LVD1RI) is set to 1 (selecting generation of a reset in response to detection of a low voltage) in the voltage monitoring 1 circuit control register 0 (LVD1CR0), the RSTSR0.LVD1RF flag is set to 1 and the voltage-detection circuit generates a voltage...
Page 145: Independent Watchdog Timer Reset
RX23W Group 6. Resets 6.3.4 Independent Watchdog Timer Reset Independent watchdog timer reset is an internal reset generated by the independent watchdog timer. Output of the independent watchdog timer reset from the independent watchdog timer can be selected by setting the IWDT reset control register (IWDTRCR) and option function select register 0 (OFS0).
Page 146: Determination Of Cold/Warm Start
RX23W Group 6. Resets 6.3.7 Determination of Cold/Warm Start By reading the CWSF flag in RSTSR1, the type of reset processing caused can be identified; that is, whether a power-on reset has caused the reset processing (cold start) or a reset signal input during operation has caused the reset processing (warm start).
Page 147: Determination Of Reset Generation Source
RX23W Group 6. Resets 6.3.8 Determination of Reset Generation Source Reading RSTSR0 and RSTSR2 determines which reset was used to execute the reset exception handling. Figure 6.4 shows an example of the flow to identify a reset generation source. Reset exception handling RSTSR2.
Page 148: Option-Setting Memory (Ofsm)
RX23W Group 7. Option-Setting Memory (OFSM) Option-Setting Memory (OFSM) Overview Option-setting memory (OFSM) refers to a set of registers that are provided for selecting the state of the microcontroller after a reset. The option-setting memory is allocated in the ROM. Figure 7.1 shows the option-setting memory area.
Page 149: Register Descriptions
RX23W Group 7. Option-Setting Memory (OFSM) Register Descriptions 7.2.1 Option Function Select Register 0 (OFS0) Address(es): OFSM.OFS0 FFFF FF8Ch WDTRS WDTTOPS[1:0] WDTST — — — WDTRPSS[1:0] WDTRPES[1:0] WDTCKS[3:0] — TIRQS Value after reset: The value set by the user* IWDTS IWDTR IWDTTOPS[1:0] IWDTS —...
Page 150 RX23W Group 7. Option-Setting Memory (OFSM) Symbol Bit Name Description b19, b18 WDTTOPS[1:0] WDT Timeout Period Select b19 b18 0 0: 1024 cycles (03FFh) 0 1: 4096 cycles (0FFFh) 1 0: 8192 cycles (1FFFh) 1 1: 16384 cycles (3FFFh) b23 to b20 WDTCKS[3:0] WDT Clock Frequency 0 0 0 1: Divide-by-4...
Page 151 RX23W Group 7. Option-Setting Memory (OFSM) counted by the counter. The value of the window end position must be smaller than the value of the window start position (window start position > window end position). If the value for the window end position is greater than the value for the window start position, only the value for the window start position is effective.
Page 152 RX23W Group 7. Option-Setting Memory (OFSM) WDTRPSS[1:0] Bits (WDT Window Start Position Select) These bits select the position where the window for the down-counter starts as 25%, 50%, 75%, or 100% of the value being counted (the point at which counting starts is 100% and the point at which an underflow occurs is 0%). The interval between the positions where the window starts and ends becomes the period in which refreshing is possible, and refreshing is not possible outside this period.
Page 153: Option Function Select Register 1 (Ofs1)
RX23W Group 7. Option-Setting Memory (OFSM) 7.2.2 Option Function Select Register 1 (OFS1) Address(es): OFSM.OFS1 FFFF FF88h, (FFFF 7F88h)* — — — — — — — — — — — — — — — — Value after reset: The value set by the user* HOCO FASTS —...
Page 154: Endian Select Register (Mde)
RX23W Group 7. Option-Setting Memory (OFSM) HOCOEN Bit (HOCO Oscillation Enable) This bit selects whether the HOCO oscillation is effective or not after a reset. Setting the HOCOEN bit to 0 allows the HOCO oscillation to be started before the CPU starts operation, and therefore reduces the wait time for oscillation stabilization.
Page 155: Usage Note
RX23W Group 7. Option-Setting Memory (OFSM) Usage Note 7.3.1 Setting Example of Option-Setting Memory Since the option-setting memory is allocated in the ROM, values cannot be written by executing instructions. Write appropriate values when writing the program. Examples of the settings are shown below. ...
Page 156: Voltage Detection Circuit (Lvdab)
RX23W Group 8. Voltage Detection Circuit (LVDAb) Voltage Detection Circuit (LVDAb) The voltage detection circuit (LVD) monitors the voltage level input to the VCC pin using a program. Overview In voltage detection 0, the detection voltage can be selected from three levels using option function select register 1 (OFS1).
Page 157 RX23W Group 8. Voltage Detection Circuit (LVDAb) Level selection LVDAS circuit (3 levels) Voltage detection 0 reset signal Analog noise filter VDSEL[1:0] Internal reference voltage  Vdet0 (for detecting Vdet0) Level selection LVD1E circuit (10 levels) LVD1CMPE Voltage detection 1 signal Analog noise filter...
Page 158: Register Descriptions
RX23W Group 8. Voltage Detection Circuit (LVDAb) Register Descriptions 8.2.1 Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1) Address(es): 0008 00E0h LVD1IR LVD1IDTSEL[1: — — — — — QSEL Value after reset: Symbol Bit Name Description b1, b0 LVD1IDTSEL Voltage Monitoring 1 Interrupt b1 b0 0 0: When VCC ...
Page 159: Voltage Monitoring 1 Circuit Status Register (Lvd1Sr)
RX23W Group 8. Voltage Detection Circuit (LVDAb) 8.2.2 Voltage Monitoring 1 Circuit Status Register (LVD1SR) Address(es): 0008 00E1h LVD1M LVD1D — — — — — — Value after reset: Symbol Bit Name Description LVD1DET Voltage Monitoring 1 Voltage Change 0: Not detected R/(W) Detection Flag 1: Vdet1 passage detection...
Page 160: Voltage Monitoring Circuit Control Register (Lvcmpcr)
RX23W Group 8. Voltage Detection Circuit (LVDAb) 8.2.3 Voltage Monitoring Circuit Control Register (LVCMPCR) Address(es): 0008 C297h — — LVD1E — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 0. The write value should be 0. LVD1E Voltage Detection 1 Enable 0: Voltage detection 1 circuit disabled...
Page 161: Voltage Detection Level Select Register (Lvdlvlr)
RX23W Group 8. Voltage Detection Circuit (LVDAb) 8.2.4 Voltage Detection Level Select Register (LVDLVLR) Address(es): 0008 C298h — — — — LVD1LVL[3:0] Value after reset: Symbol Bit Name Description b3 to b0 LVD1LVL[3:0] Voltage Detection 1 Level Select 0 1 0 0: 3.10 V (Standard voltage during drop in voltage) 0 1 0 1: 3.00 V 0 1 1 0: 2.90 V...
Page 162: Voltage Monitoring 1 Circuit Control Register 0 (Lvd1Cr0)
RX23W Group 8. Voltage Detection Circuit (LVDAb) 8.2.5 Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0) Address(es): 0008 C29Ah LVD1R LVD1C LVD1RI LVD1RI — — — — Value after reset: x: Undefined Symbol Bit Name Description LVD1RIE Voltage Monitoring 1 Interrupt/Reset 0: Disabled Enable 1: Enabled...
Page 163: Vcc Input Voltage Monitor
RX23W Group 8. Voltage Detection Circuit (LVDAb) VCC Input Voltage Monitor 8.3.1 Monitoring Vdet0 Monitoring Vdet0 is not possible. 8.3.2 Monitoring Vdet1 After making the following settings, the LVD1SR.LVD1MON flag can be used to monitor the results of comparison by voltage monitor 1.
Page 164: Reset From Voltage Monitor 0
RX23W Group 8. Voltage Detection Circuit (LVDAb) Reset from Voltage Monitor 0 When using the reset from voltage monitor 0, clear the voltage detection 0 circuit start bit (OFS1.LVDAS) to 0 (enabling the voltage monitor 0 reset after a reset). Figure 8.3 shows an example of operations for a voltage monitoring 0 reset.
Page 165: Interrupt And Reset From Voltage Monitoring 1
RX23W Group 8. Voltage Detection Circuit (LVDAb) Interrupt and Reset from Voltage Monitoring 1 Table 8.2 shows the procedures for setting bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset. Table 8.3 shows the procedures for stopping bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset.
Page 166 RX23W Group 8. Voltage Detection Circuit (LVDAb) Vdet1 Lower limit on VCC voltage (VCCmin) Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitoring 1 interrupt request Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 00b (when rise is detected).
Page 167: Event Link Output
RX23W Group 8. Voltage Detection Circuit (LVDAb) Event Link Output The LVD can output the event signals to the event link controller (ELC). (1) Vdet1 passage detection event output The LVD outputs the event signal when it is detected that the voltage has passed the Vdet1 voltage while both the voltage detection 1 circuit and the voltage monitoring 1 circuit comparison result output are enabled.
Page 168: Clock Generation Circuit
RX23W Group 9. Clock Generation Circuit Clock Generation Circuit Overview This MCU incorporates a clock generation circuit. Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock generation circuit. Table 9.1 Specifications of Clock Generation Circuit (1/2) Item Specification...
Page 169 RX23W Group 9. Clock Generation Circuit Table 9.1 Specifications of Clock Generation Circuit (2/2) Item Specification High-speed on-chip oscillator Oscillation frequency: 32 and 54 MHz (HOCO) Low-speed on-chip oscillator Oscillation frequency: 4 MHz (LOCO) IWDT-dedicated on-chip oscillator Oscillation frequency: 15 kHz ...
Page 170 RX23W Group 9. Clock Generation Circuit SCKCR FCK[3:0] UPLIDIV[1:0] USTC[5:0] UPLLCR UPLLCR FlashIF clock (FCLK) To FlashIF Frequency divider circuit SCKCR ICK[3:0] PLIDIV[1:0] STC[5:0] System clock (ICLK) PLLCR PLLCR To CPU, DMAC, DTC, ROM, and RAM Frequency Frequency divider circuit PCKA[3:0], PCKB[3:0], divider SCKCR...
Page 171 RX23W Group 9. Clock Generation Circuit Table 9.2 lists the I/O pins of the clock generation circuit. Table 9.2 I/O Pins of Clock Generation Circuit Pin Name Description XTAL Output These pins are used to connect a crystal. The EXTAL pin can also be used to input an external clock.
Page 172: Register Descriptions
RX23W Group 9. Clock Generation Circuit Register Descriptions 9.2.1 System Clock Control Register (SCKCR) Address(es): 0008 0020h FCK[3:0] ICK[3:0] — — — — — — — — Value after reset: PCKA[3:0] PCKB[3:0] — — — — PCKD[3:0] Value after reset: Symbol Bit Name Description...
Page 173 RX23W Group 9. Clock Generation Circuit Symbol Bit Name Description b31 to b28 FCK[3:0] FlashIF Clock (FCLK) 0 0 0 0: ×1 Select 0 0 0 1: ×1/2 0 0 1 0: ×1/4 0 0 1 1: ×1/8 0 1 0 0: ×1/16 0 1 0 1: ×1/32 0 1 1 0: ×1/64 Settings other than above are prohibited.
Page 174: System Clock Control Register 3 (Sckcr3)
RX23W Group 9. Clock Generation Circuit 9.2.2 System Clock Control Register 3 (SCKCR3) Address(es): 0008 0026h — — — — — CKSEL[2:0] — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 175: Pll Control Register (Pllcr)
RX23W Group 9. Clock Generation Circuit 9.2.3 PLL Control Register (PLLCR) Address(es): 0008 0028h — — STC[5:0] — — — — — — PLIDIV[1:0] Value after reset: Symbol Bit Name Description b1, b0 PLIDIV[1:0] PLL Input Frequency b1 b0 0 0: ×1 Division Ratio Select 0 1: ×1/2 1 0: ×1/4...
Page 176: Pll Control Register 2 (Pllcr2)
RX23W Group 9. Clock Generation Circuit 9.2.4 PLL Control Register 2 (PLLCR2) Address(es): 0008 002Ah — — — — — — — PLLEN Value after reset: Symbol Bit Name Description PLLEN PLL Stop Control 0: PLL is operating. 1: PLL is stopped. b7 to b1 —...
Page 177: Usb-Dedicated Pll Control Register (Upllcr)
RX23W Group 9. Clock Generation Circuit 9.2.5 USB-dedicated PLL Control Register (UPLLCR) Address(es): 0008 002Ch UCKUP — — USTC[5:0] — — — — — UPLIDIV[1:0] LLSEL Value after reset: Symbol Bit Name Description b1, b0 UPLIDIV[1:0] USB-dedicated PLL Input b1 b0 0 0: ×1 Frequency Division Ratio Select 0 1: ×1/2...
Page 178: Usb-Dedicated Pll Control Register 2 (Upllcr2)
RX23W Group 9. Clock Generation Circuit 9.2.6 USB-dedicated PLL Control Register 2 (UPLLCR2) Address(es): 0008 002Eh UPLLE — — — — — — — Value after reset: Symbol Bit Name Description UPLLEN USB-dedicated PLL Stop 0: USB-dedicated PLL is operating. Control 1: USB-dedicated PLL is stopped.
Page 179: Main Clock Oscillator Control Register (Mosccr)
RX23W Group 9. Clock Generation Circuit 9.2.7 Main Clock Oscillator Control Register (MOSCCR) Address(es): 0008 0032h — — — — — — — MOSTP Value after reset: Symbol Bit Name Description MOSTP Main Clock Oscillator Stop 0: Main clock oscillator is operating. 1: Main clock oscillator is stopped.
Page 180: Sub-Clock Oscillator Control Register (Sosccr)
RX23W Group 9. Clock Generation Circuit 9.2.8 Sub-Clock Oscillator Control Register (SOSCCR) Address(es): 0008 0033h — — — — — — — SOSTP Value after reset: Symbol Bit Name Description SOSTP Sub-Clock Oscillator Stop 0: Sub-clock oscillator is operating. 1: Sub-clock oscillator is stopped. b7 to b1 —...
Page 181: Low-Speed On-Chip Oscillator Control Register (Lococr)
RX23W Group 9. Clock Generation Circuit 9.2.9 Low-Speed On-Chip Oscillator Control Register (LOCOCR) Address(es): 0008 0034h — — — — — — — LCSTP Value after reset: Symbol Bit Name Description LCSTP LOCO Stop 0: LOCO is operating. 1: LOCO is stopped. b7 to b1 —...
Page 182: Iwdt-Dedicated On-Chip Oscillator Control Register (Ilococr)
RX23W Group 9. Clock Generation Circuit 9.2.10 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) Address(es): 0008 0035h — — — — — — — ILCSTP Value after reset: Symbol Bit Name Description ILCSTP IWDT-Dedicated On-Chip 0: IWDT-dedicated on-chip oscillator is operating. Oscillator Stop 1: IWDT-dedicated on-chip oscillator is stopped.
Page 183: High-Speed On-Chip Oscillator Control Register (Hococr)
RX23W Group 9. Clock Generation Circuit 9.2.11 High-Speed On-Chip Oscillator Control Register (HOCOCR) Address(es): 0008 0036h — — — — — — — HCSTP Value after reset: Symbol Bit Name Description HCSTP HOCO Stop 0: HOCO is operating. 1: HOCO is stopped. b7 to b1 —...
Page 184: High-Speed On-Chip Oscillator Control Register 2 (Hococr2)
RX23W Group 9. Clock Generation Circuit 9.2.12 High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) Address(es): 0008 0037h — — — — — — HCFRQ[1:0] Value after reset: Symbol Bit Name Description b1, b0 HCFRQ[1:0] HOCO Frequency Setting b1 b0 0 0: 32 MHz 1 1: 54 MHz Settings other than above are prohibited.
Page 185: Oscillation Stabilization Flag Register (Oscovfsr)
RX23W Group 9. Clock Generation Circuit 9.2.13 Oscillation Stabilization Flag Register (OSCOVFSR) Address(es): 0008 003Ch UPLOV MOOV — — — HCOVF PLOVF — Value after reset: 0/1* Symbol Bit Name Description MOOVF Main Clock Oscillation 0: Main clock is stopped Stabilization Flag 1: Oscillation is stable and the clock can be used as the system clock* —...
Page 186 RX23W Group 9. Clock Generation Circuit HCOVF Flag (HOCO Clock Oscillation Stabilization Flag) This flag indicates whether oscillation of the HOCO clock is stable. [Setting condition]  After the HOCOCR.HCSTP bit is set to 0 (HOCO is operating) when the HCSTP bit is 1 (HOCO is stopped), supply of the HOCO clock is started to the MCU internally.
Page 187: Oscillation Stop Detection Control Register (Ostdcr)
RX23W Group 9. Clock Generation Circuit 9.2.14 Oscillation Stop Detection Control Register (OSTDCR) Address(es): 0008 0040h OSTDI OSTDE — — — — — — Value after reset: Symbol Bit Name Description OSTDIE Oscillation Stop Detection 0: The oscillation stop detection interrupt is disabled. Oscillation stop Interrupt Enable detection is not notified to the POE.
Page 188: Oscillation Stop Detection Status Register (Ostdsr)
RX23W Group 9. Clock Generation Circuit 9.2.15 Oscillation Stop Detection Status Register (OSTDSR) Address(es): 0008 0041h — — — — — — — OSTDF Value after reset: Symbol Bit Name Description OSTDF Oscillation Stop Detection Flag 0: The main clock oscillation stop has not been detected. R/(W) 1: The main clock oscillation stop has been detected.
Page 189: Main Clock Oscillator Wait Control Register (Moscwtcr)
RX23W Group 9. Clock Generation Circuit 9.2.16 Main Clock Oscillator Wait Control Register (MOSCWTCR) Address(es): 0008 00A2h — — — MSTS[4:0] Value after reset: Symbol Bit Name Description b4 to b0 MSTS[4:0] Main Clock Oscillator Wait Time 0 0 0 0 0: Wait time = 2 cycles (0.5 μs) 0 0 0 0 1: Wait time = 1024 cycles (256 μs) 0 0 0 1 0: Wait time = 2048 cycles (512 μs) 0 0 0 1 1: Wait time = 4096 cycles (1.024 ms)
Page 190: Clkout Output Control Register (Ckocr)
RX23W Group 9. Clock Generation Circuit 9.2.17 CLKOUT Output Control Register (CKOCR) Address(es): 0008 003Eh CKOST CKODIV[2:0] CKOSEL[3:0] — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 — Reserved These bits are read as 0. The write value should be 0. b11 to b8 CKOSEL[3:0] CLKOUT Output Source Select...
Page 191: Main Clock Oscillator Forced Oscillation Control Register (Mofcr)
RX23W Group 9. Clock Generation Circuit 9.2.18 Main Clock Oscillator Forced Oscillation Control Register (MOFCR) Address(es): 0008 C293h MOSEL MODR — — — — — — Value after reset: Symbol Bit Name Description b4 to b0 — Reserved These bits are read as 0. The write value should be 0. VCC ...
Page 192: Memory Wait Cycle Setting Register (Memwait)
RX23W Group 9. Clock Generation Circuit 9.2.19 Memory Wait Cycle Setting Register (MEMWAIT) Address(es): 0008 0031h MEMW — — — — — — — Value after reset: Symbol Bit Name Description MEMWAIT Memory Wait Cycle Setting* 0: No wait states 1: Wait states b7 to b1 —...
Page 193 RX23W Group 9. Clock Generation Circuit Start Change to high-speed mode MEMWAIT.MEMWAIT bit = 1 MEMWAIT.MEMWAIT bit = 1? Change ICLK frequency to higher than 32 MHz Note 1. Resetting is not necessary in high-speed mode. Figure 9.2 Example of MEMWAIT Bit Setting Procedure When Changing ICLK Frequency to Higher than 32 Start Change ICLK frequency to lower than 32 MHz...
Page 194: Low-Speed On-Chip Oscillator Trimming Register (Locotrr)
RX23W Group 9. Clock Generation Circuit 9.2.20 Low-Speed On-Chip Oscillator Trimming Register (LOCOTRR) Address(es): 0008 0060h — — — LOCOTRD[4:0] Value after reset: Symbol Bit Name Description b4 to b0 LOCOTRD[ Low-Speed On-Chip Oscillator 1 0 0 0 0: -16 (Frequency: Low) 4:0] Frequency Adjustment 1 0 0 0 1: -15...
Page 195: High-Speed On-Chip Oscillator Trimming Register N (Hocotrrn) (N = 0, 3)
RX23W Group 9. Clock Generation Circuit 9.2.22 High-Speed On-Chip Oscillator Trimming Register n (HOCOTRRn) (n = 0, 3) Address(es): HOCOTRR0 0008 0068h, HOCOTRR3 0008 006Bh — — HOCOTRD[5:0] Value after reset: Symbol Bit Name Description b5 to b0 HOCOTRD[ High-Speed On-Chip Oscillator 0 0 0 0 0 0: 0 (Frequency: Low) 5:0] Frequency Adjustment...
Page 196: Main Clock Oscillator
RX23W Group 9. Clock Generation Circuit Main Clock Oscillator There are two ways of supplying the clock signal from the main clock oscillator: connecting an oscillator or the input of an external clock signal. 9.3.1 Connecting a Crystal Figure 9.4 shows an example of connecting a crystal. A damping resistor (Rd) should be added, if necessary.
Page 197: External Clock Input
RX23W Group 9. Clock Generation Circuit 9.3.2 External Clock Input Figure 9.6 shows connection of an external clock. If operation is to be driven by an external clock, set the MOFCR.MOSEL bit to 1 and leave the XTAL pin open-circuit. EXTAL External clock input Open...
Page 198: Sub-Clock Oscillator
RX23W Group 9. Clock Generation Circuit Sub-Clock Oscillator The only way of supplying the clock signal from the sub-clock oscillator is connecting a crystal. 9.4.1 Connecting 32.768-kHz Crystal To supply a clock to the sub-clock oscillator, connect a 32.768-kHz crystal, as shown in Figure 9.7 . A damping resistor Rd should be added, if necessary.
Page 199: Handling Of Pins When Sub-Clock Is Not Used
RX23W Group 9. Clock Generation Circuit 9.4.2 Handling of Pins When Sub-Clock is Not Used If the sub-clock is not in use, connect the XCIN pin to VSS via a resistor (to pull VSS down) and leave the XCOUT pin open-circuit as shown in Figure 9.9 .
Page 200: Dedicated Clock Oscillator For Bluetooth
(Rf) to the oscillator is required, insert Rf between XTAL1_RF and XTAL2_RF according to the instructions. To control the oscillator, use the Bluetooth middleware provided by Renesas. The Bluetooth middleware is also able to control the settings of the on-chip variable capacitors, CL1 and CL2, to adjust the frequency of oscillation. Adjustment of the frequency of the Bluetooth-dedicated clock oscillator is explained in the application note Procedure for Adjusting the Frequency of the Bluetooth-Dedicated Clock Oscillator (R01AN4762).
Page 201: Oscillation Stop Detection Function
RX23W Group 9. Clock Generation Circuit Oscillation Stop Detection Function 9.6.1 Oscillation Stop Detection and Operation after Detection The oscillation stop detection function is used to detect the main clock oscillator stop and to supply LOCO clock pulses from the low-speed on-chip oscillator as the system clock source instead of the main clock. An oscillation stop detection interrupt request can be generated when an oscillation stop is detected.
Page 202: Oscillation Stop Detection Interrupts
RX23W Group 9. Clock Generation Circuit Start Switch to SCKCR3.CKSEL[2:0] = 000b (LOCO) Setting OSTDCR.OSTDIE = 0 Reading OSTDSR.OSTDF = 1 Setting OSTDSR.OSTDF = 0 OSTDSR.OSTDF = 0 Try again? Switch to SCKCR3.CKSEL[2:0] = 010b (main clock oscillator) Note: On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation circuit must be removed on the user system to allow the return of oscillation.
Page 203: Pll Circuit
RX23W Group 9. Clock Generation Circuit PLL Circuit The PLL circuit has a function to multiply the frequency from the oscillator. Internal Clock Clock sources of internal clock signals are the main clock, sub-clock, HOCO clock, LOCO clock, PLL clock, USB-dedicated PLL clock, and dedicated low-speed clock for the IWDT.
Page 204: Usb Clock
9.8.10 Clocks for BLE The Bluetooth-dedicated clock (BLECLK) and the Bluetooth-dedicated low-speed clock (BLELOCO) are the operating clocks for the BLE. To control these clocks, use the Bluetooth middleware provided by Renesas. 9.8.11 Low-Power Timer Clock The low-power timer clock (LPTCLK) is an operating clock for the low-power timer. The LPTCLK clocks include a clock generated by the sub-clock oscillator and a clock generated by the IWDT-dedicated on-chip oscillator.
Page 205: Usage Notes
RX23W Group 9. Clock Generation Circuit Usage Notes 9.9.1 Notes on Clock Generation Circuit (1) The frequencies of the system clock (ICLK), peripheral module clocks (PCLKA, PCLKB, and PCLKD), and FlashIF clock (FCLK) supplied to each module can be selected by the SCKCR register. Each frequency should meet the following: Select each frequency that is within the operation guaranteed range of clock cycle time (tcyc) specified in AC characteristics of electrical characteristics.
Page 206: Notes On Resonator Connection Pins
RX23W Group 9. Clock Generation Circuit 9.9.4 Notes on Resonator Connection Pins When the main clock is not used, the EXTAL and XTAL pins can be used as general ports P36 and P37. When using these pins as general ports, be sure to stop the main clock (MOSCCR.MOSTP = 1). However, do not use the EXTAL and XTAL pins as general ports P36 and P37 in a system that uses the main clock.
Page 207 RX23W Group 9. Clock Generation Circuit  When using the sub-clock only as the count source of the realtime clock, perform initial settings according to the flowchart example shown in Figure 9.15 . After that, perform the clock setting procedure shown in section 28.3.2, Clock and Count Mode Setting Procedure .
Page 208 RX23W Group 9. Clock Generation Circuit  When using the sub-clock only as the system clock, perform initial settings according to the flowchart example shown in Figure 9.16 . Sub-clock SOSCCR. RCR3. Start oscillation state SOSTP RTCEN Set the SOSCCR.SOSTP bit to 1 (sub-clock oscillator is stopped). Oscillating Undefined Read the SOSCCR.SOSTP bit and confirm that it is 1.
Page 209 RX23W Group 9. Clock Generation Circuit  When not using the sub-clock, perform initial settings according to the flowchart example in Figure 9.17 . Sub-clock SOSCCR. RCR3. Start oscillation state SOSTP RTCEN Set the SOSCCR.SOSTP bit to 1 (sub-clock oscillator is stopped). Undefined Read the SOSCCR.SOSTP bit and confirm that it is 1.
Page 210: Clock Frequency Accuracy Measurement Circuit (Cac)
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) Clock Frequency Accuracy Measurement Circuit (CAC) 10.1 Overview The clock frequency accuracy measurement circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range.
Page 211 RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) DFS[1:0] CACREFE DFS[1:0] CACREF Digital filter RSCS[2:0] RCDS[1:0] EDGES[1:0] 1/32 Measurement 1/128 Edge detection reference circuit 1/1024 clock select circuit 1/8192 Valid edge signal FMCS[2:0] TCSS[1:0] Measurement target clock Main clock CFME Sub-clock Count source...
Page 212: Register Descriptions
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2 Register Descriptions 10.2.1 CAC Control Register 0 (CACR0) Address(es): 0008 B000h — — — — — — — CFME Value after reset: Symbol Bit Name Description CFME Clock Frequency Measurement Enable 0: Clock frequency measurement is disabled.
Page 213: Cac Control Register 1 (Cacr1)
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.2 CAC Control Register 1 (CACR1) Address(es): 0008 B001h CACRE EDGES[1:0] TCSS[1:0] FMCS[2:0] Value after reset: Symbol Bit Name Description CACREFE CACREF Pin Input Enable 0: CACREF pin input is disabled. 1: CACREF pin input is enabled.
Page 214: Cac Control Register 2 (Cacr2)
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.3 CAC Control Register 2 (CACR2) Address(es): 0008 B002h DFS[1:0] RCDS[1:0] RSCS[2:0] Value after reset: Symbol Bit Name Description Reference Signal Select 0: CACREF pin input 1: Internal clock (internally generated signal) b3 to b1 RSCS[2:0] Measurement Reference Clock...
Page 215: Cac Interrupt Request Enable Register (Caicr)
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.4 CAC Interrupt Request Enable Register (CAICR) Address(es): 0008 B003h OVFFC MENDF FERRF OVFIE MENDI FERRI — — Value after reset: Symbol Bit Name Description FERRIE Frequency Error Interrupt Request 0: Frequency error interrupt request is disabled. Enable 1: Frequency error interrupt request is enabled.
Page 216: Cac Status Register (Castr)
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.5 CAC Status Register (CASTR) Address(es): 0008 B004h — — — — — OVFF MENDF FERRF Value after reset: Symbol Bit Name Description FERRF Frequency Error Flag 0: The clock frequency is within the range corresponding to the settings.
Page 217: Cac Upper-Limit Value Setting Register (Caulvr)
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.6 CAC Upper-Limit Value Setting Register (CAULVR) Address(es): 0008 B006h Value after reset: CAULVR is a 16-bit readable/writable register that specifies the upper-limit value of the counter used for measuring the frequency.
Page 218: Operation
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.3 Operation 10.3.1 Measuring Clock Frequency The clock frequency accuracy measurement circuit measures the clock frequency using the CACREF pin input or the internal clock as a reference. Figure 10.2 shows an operating example of the clock frequency accuracy measurement circuit.
Page 219: Digital Filtering Of Signals On The Cacref Pin
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. Also, the MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt is generated. (5) When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of CAULVR and CALLVR.
Page 220: Usage Notes
RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.5 Usage Notes 10.5.1 Module Stop Function Setting CAC operation can be disabled or enabled using module stop control register C (MSTPCRC). The initial setting is for the CAC to be halted. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 221: Low Power Consumption
RX23W Group 11. Low Power Consumption Low Power Consumption 11.1 Overview This MCU has several functions for reducing power consumption, by setting clock dividers, stopping modules, changing to low power consumption mode in normal operation, and changing to operating power control mode. Table 11.1 lists the specifications of low power consumption functions, and Table 11.2 lists the conditions to change to low power consumption modes, states of the CPU and peripheral modules, and the method for exiting each mode.
Page 222 RX23W Group 11. Low Power Consumption Table 11.2 Operating Conditions of Each Power Consumption Mode Entering and Exiting Low Power Consumption Modes and Operating States Sleep Mode Deep Sleep Mode Software Standby Mode Entry trigger Control register + instruction Control register + instruction Control register + instruction Exit trigger Interrupt...
Page 223 RX23W Group 11. Low Power Consumption Reset state Normal operation mode (Program execution state) WAIT instruction* WAIT instruction* WAIT instruction* SSBY = 0 All interrupts Interrupt* All interrupts MSTPCRA.MSTPA28 = 1 SSBY = 1 SSBY = 0 MSTPCRC.DSLPE = 1 Software standby Sleep mode Deep sleep mode...
Page 224 RX23W Group 11. Low Power Consumption Reset state Software Software Deep sleep mode Deep sleep mode standby mode standby mode Exit the reset state High-speed Middle-speed Sleep mode Sleep mode operating mode operating mode Set the OPCCR register the SOPCCR the SOPCCR register register...
Page 225: Register Descriptions
RX23W Group 11. Low Power Consumption 11.2 Register Descriptions 11.2.1 Standby Control Register (SBYCR) Address(es): 0008 000Ch SSBY — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b14 to b0 —...
Page 226: Module Stop Control Register A (Mstpcra)
RX23W Group 11. Low Power Consumption 11.2.2 Module Stop Control Register A (MSTPCRA) Address(es): 0008 0010h MSTPA MSTPA MSTPA — — — — — — — — — — — — — Value after reset: MSTPA MSTPA MSTPA MSTPA MSTPA MSTPA —...
Page 227: Module Stop Control Register B (Mstpcrb)
RX23W Group 11. Low Power Consumption 11.2.3 Module Stop Control Register B (MSTPCRB) Address(es): 0008 0014h MSTPB MSTPB MSTPB MSTPB MSTPB MSTPB MSTPB — — — — — — — — — Value after reset: MSTPB MSTPB MSTPB MSTPB MSTPB —...
Page 228 RX23W Group 11. Low Power Consumption Symbol Bit Name Description b29 to b27 — Reserved These bits are read as 1. The write value should be 1. MSTPB30 Serial Communication Target module: SCI1 Interface 1 Module Stop 0: This module clock is enabled 1: This module clock is disabled —...
Page 229: Module Stop Control Register C (Mstpcrc)
RX23W Group 11. Low Power Consumption 11.2.4 Module Stop Control Register C (MSTPCRC) Address(es): 0008 0018h MSTPC MSTPC MSTPC DSLPE — — — — — — — — — — — — Value after reset: MSTPC — — — — —...
Page 230: Module Stop Control Register D (Mstpcrd)
RX23W Group 11. Low Power Consumption 11.2.5 Module Stop Control Register D (MSTPCRD) Address(es): 0008 001Ch MSTPD MSTPD — — — — — — — — — — — — — — Value after reset: MSTPD MSTPD — — — —...
Page 231: Operating Power Control Register (Opccr)
RX23W Group 11. Low Power Consumption 11.2.6 Operating Power Control Register (OPCCR) Address(es): 0008 00A0h OPCM — — — — OPCM[2:0] Value after reset: Symbol Bit Name Description b2 to b0 OPCM[2:0] Operating Power Control 0 0 0: High-speed operating mode Mode Select 0 1 0: Middle-speed operating mode Settings other than above are prohibited.
Page 232: Sub Operating Power Control Register (Sopccr)
RX23W Group 11. Low Power Consumption 11.2.7 Sub Operating Power Control Register (SOPCCR) Address(es): 0008 00AAh SOPC SOPC — — — — — — MTSF Value after reset: Symbol Bit Name Description SOPCM Sub Operating Power 0: High-speed operating mode or middle-speed operating mode* Control Mode Select 1: Low-speed operating mode b3 to b1...
Page 233 RX23W Group 11. Low Power Consumption SOPCMTSF Flag (Sub Operating Power Control Mode Transition Status Flag) The SOPCMTSF flag indicates the switching control state when the sub operating power control mode is switched. This flag becomes 1 when the value of the SOPCM bit is rewritten, and 0 when mode transition is completed. Read this flag and confirm that it is 0 before proceeding to the next processing.
Page 234 RX23W Group 11. Low Power Consumption  High-Speed Operating Mode The maximum operating frequency during FLASH read is 54 MHz for ICLK, PCLKA, and PCLKD; 32 MHz for PCLKB, and FCLK. The operating voltage range is 1.8 to 3.6 V during FLASH read. However, the maximum operating frequency during FLASH read is 16 MHz for ICLK, FCLK, PCLKA, and PCLKB, and 32 MHz for PCLKD when the operating voltage is 2.4 V or larger and smaller than 2.7 V.
Page 235 RX23W Group 11. Low Power Consumption  Middle-Speed Operating Mode As compared to high-speed operating mode, this mode reduces power consumption for low-speed operation. The maximum operating frequency during FLASH read is 12 MHz for ICLK, FCLK, PCLKA, PCLKB, and PCLKD. The operating voltage range is 1.8 to 3.6 V during FLASH read.
Page 236 RX23W Group 11. Low Power Consumption  Low-Speed Operating Mode A transition to low-speed operating mode is set by writing 1 to the SOPCM bit in the SOPCCR register. The setting of the OPCM[2:0] bits cannot be modified during low-speed operating mode. This mode is used only for the sub oscillator of 32.768 kHz.
Page 237: Sleep Mode Return Clock Source Switching Register (Rstckcr)
RX23W Group 11. Low Power Consumption 11.2.8 Sleep Mode Return Clock Source Switching Register (RSTCKCR) Address(es): 0008 00A1h RSTCK — — — — RSTCKSEL[2:0] Value after reset: Symbol Bit Name Description b2 to b0 RSTCKSEL Sleep Mode Return Clock 0 0 0: LOCO is selected [2:0] Source Select 0 0 1: HOCO is selected*...
Page 238 RX23W Group 11. Low Power Consumption RSTCKEN Bit (Sleep Mode Return Clock Source Switching Enable) The RSTCKEN bit enables or disables clock source switching when sleep mode is exited. The clock source can be switched when exiting sleep mode only while the sub-clock oscillator is selected as the clock for entering sleep mode.
Page 239: Reducing Power Consumption By Switching Clock Signals
RX23W Group 11. Low Power Consumption 11.3 Reducing Power Consumption by Switching Clock Signals The clock frequency can change by setting the SCKCR.FCK[3:0], ICK[3:0], PCKA[3:0], PCKB[3:0], and PCKD[3:0] bits. The CPU, DMAC, DTC, ROM, and RAM clocks can be set by the ICK[3:0] bits. The peripheral module clocks can be set by the PCKA[3:0], PCKB[3:0], and PCKD[3:0] bits.
Page 240 RX23W Group 11. Low Power Consumption  Example 2: From high-speed/middle-speed operating mode to low-speed operating mode (High-speed operation in high-speed operating mode/middle-speed operation in middle-speed operating mode) ↓ Set the frequency of each clock to lower than the maximum operating frequency for low-speed operating mode ↓...
Page 241: Low Power Consumption Modes
RX23W Group 11. Low Power Consumption 11.6 Low Power Consumption Modes 11.6.1 Sleep Mode 11.6.1.1 Entry to Sleep Mode When the WAIT instruction is executed while the SBYCR.SSBY bit is 0, the CPU enters sleep mode. In sleep mode, the CPU stops operating but the contents of its internal registers are retained.
Page 242: Exit From Sleep Mode
RX23W Group 11. Low Power Consumption 11.6.1.2 Exit from Sleep Mode Exit from sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow.  Initiated by an interrupt An interrupt initiates exit from sleep mode and the interrupt exception handling starts.
Page 243: Deep Sleep Mode
RX23W Group 11. Low Power Consumption 11.6.2 Deep Sleep Mode 11.6.2.1 Entry to Deep Sleep Mode When a WAIT instruction is executed with the MSTPCRC.DSLPE bit set to 1, the MSTPCRA.MSTPA28 bit set to 1, and the SBYCR.SSBY bit cleared to 0, a transition to deep sleep mode is made. In deep sleep mode, the CPU and the DMAC, DTC, ROM, and RAM clocks stop.
Page 244: Exit From Deep Sleep Mode
RX23W Group 11. Low Power Consumption 11.6.2.2 Exit from Deep Sleep Mode Exit from deep sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow. ...
Page 245: Software Standby Mode
RX23W Group 11. Low Power Consumption 11.6.3 Software Standby Mode 11.6.3.1 Entry to Software Standby Mode When a WAIT instruction is executed with the SBYCR.SSBY bit set to 1, a transition to software standby mode is made. In this mode, the CPU, on-chip peripheral functions, and all the other functions except the sub-clock oscillator stop. However, the contents of the CPU internal registers, RAM data, the states of on-chip peripheral functions, the I/O ports, and the sub-clock oscillator are retained.
Page 246: Exit From Software Standby Mode
RX23W Group 11. Low Power Consumption 11.6.3.2 Exit from Software Standby Mode Exit from software standby mode is initiated by an external pin interrupt (the NMI, IRQ0, IRQ1, IRQ4 to IRQ7), peripheral function interrupts (the RTC alarm, RTC interval, IWDT, voltage monitoring, VBATT pin voltage drop detection, USB, and ELC (LPT-dedicated interrupt)), a RES# pin reset, a power-on reset, a voltage monitoring reset, or an independent watchdog timer reset.
Page 247: Example Of Software Standby Mode Application
RX23W Group 11. Low Power Consumption 11.6.3.3 Example of Software Standby Mode Application Figure 11.6 shows an example of entry to software standby mode by the falling edge of the IRQn pin, and exit from software standby mode by the rising edge of the IRQn pin. In this example, an IRQn interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge), and then the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge).
Page 248: Usage Notes
RX23W Group 11. Low Power Consumption 11.7 Usage Notes 11.7.1 I/O Port States I/O port states are retained in software standby mode. Therefore, the supply current is not reduced if output signals are high level. 11.7.2 Module Stop State of DMAC and DTC Before setting the MSTPCRA.MSTPA28 bit to 1, set the DMAST.DMST bit of the DMAC and the DTCST.DTCST bit of the DTC to 0 to avoid activating the DMAC and DTC.
Page 249: Battery Backup Function
RX23W Group 12. Battery Backup Function Battery Backup Function 12.1 Overview When the voltage at the VCC pin is dropped, power can be supplied to the realtime clock (RTC) and the sub-clock oscillator placed in the battery backup power area from the battery backup power pin (VBATT pin). When the battery backup function is not used, connect the VBATT pin to the VCC pin and disable the battery backup function (set the VBATTCR.VBATTDIS bit to 1).
Page 250: Register Descriptions
RX23W Group 12. Battery Backup Function 12.2 Register Descriptions 12.2.1 VBATT Control Register (VBATTCR) Address(es): 0008 C29Dh VBTLV VBATT VBTLVDLVL[1:0] — — — — Value after reset: Symbol Bit Name Description VBATTDIS Battery Backup Function 0: Battery backup function enabled Disable 1: Battery backup function disabled b3 to b1...
Page 251: Vbatt Status Register (Vbattsr)
RX23W Group 12. Battery Backup Function 12.2.2 VBATT Status Register (VBATTSR) Address(es): 0008 C29Eh VBTLV VBATRL — — — — — — DMON VDETF Value after reset: x: Undefined Symbol Bit Name Description VBATRLVDETF Battery Backup Power 0: Battery backup power voltage drop (< 1.8 V) not detected R/W* Voltage Drop Detection Flag 1: Battery backup power voltage drop (<...
Page 252: Vbatt Pin Voltage Drop Detection Interrupt Control Register (Vbtlvdicr)
RX23W Group 12. Battery Backup Function 12.2.3 VBATT Pin Voltage Drop Detection Interrupt Control Register (VBTLVDICR) Address(es): 0008 C29Fh VBTLV VBTLV — — — — — — DISEL Value after reset: Symbol Bit Name Description VBTLVDIE VBATT Pin Voltage Drop Detection 0: VBATT pin voltage drop detection interrupt disabled Interrupt Enable 1: VBATT pin voltage drop detection interrupt enabled...
Page 253: Operation
RX23W Group 12. Battery Backup Function 12.3 Operation 12.3.1 Battery Backup Function When the voltage at the VCC pin is dropped, power can be supplied to the RTC and sub-clock oscillator from the VBATT pin. When the power supply reduction from the VCC pin is detected, connection to power is switched to the power supply from the VBATT pin.
Page 254: Vbatt Pin Voltage Monitoring Function
RX23W Group 12. Battery Backup Function VCC pin voltage VDETBATT VBATT pin voltage VBATT pin voltage drop VBATT pin voltage rise detected detected VBATT VBATT operating range Vdetvbt VBATT pin voltage monitor flag VBATT pin voltage  Vdetvbt VBATT pin voltage  Vdetvbt VBATT pin voltage <...
Page 255: Usage Notes
RX23W Group 12. Battery Backup Function 12.4 Usage Notes 1. When the VBATT pin is not used, connect the VBATT pin to the VCC pin. 2. When the battery backup function is not used, set the VBATTCR.VBATTDIS bit to 1 (battery backup function disabled).
Page 256: Register Write Protection Function
RX23W Group 13. Register Write Protection Function Register Write Protection Function The register write protection function protects important registers from being overwritten for in case a program runs out of control. The registers to be protected are set with the protect register (PRCR). Table 13.1 lists the association between the PRCR bits and the registers to be protected.
Page 257: Register Descriptions
RX23W Group 13. Register Write Protection Function 13.1 Register Descriptions 13.1.1 Protect Register (PRCR) Address(es): 0008 03FEh PRKEY[7:0] — — — — PRC3 PRC2 PRC1 PRC0 Value after reset: Symbol Bit Name Function PRC0 Protect Bit 0 Enables writing to the registers related to the clock generation circuit. 0: Write disabled 1: Write enabled PRC1...
Page 258: Exception Handling
RX23W Group 14. Exception Handling Exception Handling 14.1 Exception Events During execution of a program by the CPU, the occurrence of a certain event may cause execution of that program to be suspended and execution of another program to be started. Such kinds of events are called exception events. The RXv2 CPU supports eight types of exceptions.
Page 259: Undefined Instruction Exception
RX23W Group 14. Exception Handling 14.1.1 Undefined Instruction Exception An undefined instruction exception occurs when execution of an undefined instruction (an instruction not implemented) is detected. 14.1.2 Privileged Instruction Exception A privileged instruction exception occurs when execution of a privileged instruction is detected in user mode. Privileged instructions can be executed only in supervisor mode.
Page 260: Exception Handling Procedure
RX23W Group 14. Exception Handling 14.2 Exception Handling Procedure In the exception handling, part of the processing is handled automatically by hardware and part of it is handled by a program (exception handling routine) that has been written by the user. Figure 14.2 shows the processing procedure when an exception other than a reset is accepted.
Page 261 RX23W Group 14. Exception Handling When an exception is accepted, hardware processing by the RXv2 CPU is followed by access to the vector to acquire the address of the branch destination. In the vector, a vector address is allocated to each exception, and the branch destination address of the exception handling routine is written to each vector address.
Page 262: Acceptance Of Exception Events
RX23W Group 14. Exception Handling 14.3 Acceptance of Exception Events When an exception occurs, the CPU suspends the execution of the program and processing branches to the exception handling routine. 14.3.1 Acceptance Timing and Saved PC Value Table 14.1 lists the timing of acceptance and the program counter (PC) value to be saved for each exception event. Table 14.1 Acceptance Timing and Saved PC Value Acceptance...
Page 263: Vector And Site For Saving The Values In The Pc And Psw
RX23W Group 14. Exception Handling 14.3.2 Vector and Site for Saving the Values in the PC and PSW The vector for each type of exception and the site for saving the values of the program counter (PC) and processor status word (PSW) are listed in Table 14.2 .
Page 264: Hardware Processing For Accepting And Returning From Exceptions
RX23W Group 14. Exception Handling 14.4 Hardware Processing for Accepting and Returning from Exceptions This section describes the hardware processing for accepting and returning from exceptions other than a reset. (1) Hardware Pre-Processing for Accepting an Exception (a) Saving PSW ...
Page 265: Hardware Pre-Processing
RX23W Group 14. Exception Handling 14.5 Hardware Pre-Processing The hardware pre-processing from reception of each exception request to execution of the associated exception handling routine are explained below. 14.5.1 Undefined Instruction Exception 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2.
Page 266: Non-Maskable Interrupt
RX23W Group 14. Exception Handling 14.5.6 Non-Maskable Interrupt 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2. The processor mode select bit (PM), the stack pointer select bit (U), and the interrupt enable bit (I) in PSW are cleared to 0.
Page 267: Return From Exception Handling Routine
RX23W Group 14. Exception Handling 14.6 Return from Exception Handling Routine Executing the instruction listed in Table 14.3 at the end of the corresponding exception handling routine restores the values of the program counter (PC) and processor status word (PSW) that were saved on the stack or in the control registers (BPC and BPSW) immediately before the exception handling sequence.
Page 268: Interrupt Controller (Icub)
RX23W Group 15. Interrupt Controller (ICUb) Interrupt Controller (ICUb) 15.1 Overview The interrupt controller receives interrupt requests from peripheral modules and external pins, and generates an interrupt request to the CPU and a transfer request to the DTC and DMAC. Table 15.1 lists the specifications of the interrupt controller, and Figure 15.1 shows a block diagram of the interrupt controller.
Page 269 RX23W Group 15. Interrupt Controller (ICUb) Interrupt controller VBATT voltage monitoring interrupt Clock Voltage monitoring 1 interrupt generation IWDT underflow/refresh error Clock restoration request WDT underflow/refresh error circuit Clock Oscillation stop detection interrupt restoration Digital filter Detection NMI pin judgment Clock restoration enable level Non-maskable interrupt request IFLTE...
Page 270: Register Descriptions
RX23W Group 15. Interrupt Controller (ICUb) 15.2 Register Descriptions 15.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number) Address(es): ICU.IR016 0008 7010h to ICU.IR255 0008 70FFh — — — — — — — Value after reset: Symbol Bit Name Description Interrupt Status Flag 0: No interrupt request is generated...
Page 271: Interrupt Request Enable Register M (Ierm) (M = 02H To 1Fh)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.2 Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) Address(es): ICU.IER02 0008 7202h to ICU.IER1F 0008 721Fh IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Value after reset: Symbol Bit Name Description IEN0 Interrupt Request Enable 0...
Page 272: Interrupt Source Priority Register N (Iprn) (N = Interrupt Vector Number)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.3 Interrupt Source Priority Register n (IPRn) (n = interrupt vector number) Address(es): ICU.IPR000 0008 7300h to ICU.IPR255 0008 73FFh — — — — IPR[3:0] Value after reset: Symbol Bit Name Description b3 to b0 IPR[3:0] Interrupt Priority Level Select 0 0 0 0: Level 0 (interrupt disabled)*...
Page 273: Fast Interrupt Set Register (Fir)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.4 Fast Interrupt Set Register (FIR) Address(es): ICU.FIR 0008 72F0h FIEN — — — — — — — FVCT[7:0] Value after reset: Symbol Bit Name Description b7 to b0 FVCT[7:0] Fast Interrupt Vector Number Specify the vector number of an interrupt source to be a fast interrupt.
Page 274: Software Interrupt Generation Register (Swintr)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.5 Software Interrupt Generation Register (SWINTR) Address(es): ICU.SWINTR 0008 72E0h — — — — — — — SWINT Value after reset: Symbol Bit Name Description SWINT Software Interrupt Generation This bit is read as 0. Writing 1 issues a software interrupt request. R/(W) Writing 0 to this bit has no effect.
Page 275: Dtc Transfer Request Enable Register N (Dtcern) (N = Interrupt Vector Number)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.6 DTC Transfer Request Enable Register n (DTCERn) (n = interrupt vector number) Address(es): ICU.DTCER027 0008 711Bh to ICU.DTCER255 0008 71FFh — — — — — — — DTCE Value after reset: Symbol Bit Name Description DTCE DTC Transfer Request...
Page 276: Dmac Trigger Select Register M (Dmrsrm) (M = Dmac Channel Number)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.7 DMAC Trigger Select Register m (DMRSRm) (m = DMAC channel number) Address(es): ICU.DMRSR0 0008 7400h, ICU.DMRSR1 0008 7404h, ICU.DMRSR2 0008 7408h, ICU.DMRSR3 0008 740Ch DMRS[7:0] Value after reset: Symbol Bit Name Description b7 to b0 DMRS[7:0] DMAC Trigger Select These bits specify the vector number for the DMA transfer...
Page 277: Irq Control Register I (Irqcri) (I = 0, 1, And 4 To 7)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.8 IRQ Control Register i (IRQCRi) (i = 0, 1, and 4 to 7) Address(es): ICU.IRQCR0 0008 7500h, ICU.IRQCR1 0008 7501h, ICU.IRQCR4 0008 7504h to ICU.IRQCR7 0008 7507h — — — — IRQMD[1:0] — —...
Page 278: Irq Pin Digital Filter Enable Register 0 (Irqflte0)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.9 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) Address(es): ICU.IRQFLTE0 0008 7510h FLTEN FLTEN FLTEN FLTEN FLTEN FLTEN — — Value after reset: Symbol Bit Name Description FLTEN0 IRQ0 Digital Filter Enable 0: Digital filter is disabled 1: Digital filter is enabled FLTEN1 IRQ1 Digital Filter Enable...
Page 279: Irq Pin Digital Filter Setting Register 0 (Irqfltc0)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.10 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) Address(es): ICU.IRQFLTC0 0008 7514h FCLKSEL7[1:0] FCLKSEL6[1:0] FCLKSEL5[1:0] FCLKSEL4[1:0] — — FCLKSEL1[1:0] FCLKSEL0[1:0] Value after reset: Symbol Bit Name Description b1, b0 FCLKSEL0[1:0] IRQ0 Digital Filter Sampling Clock 0 0: PCLK 0 1: PCLK/8 b3, b2...
Page 280: Non-Maskable Interrupt Status Register (Nmisr)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.11 Non-Maskable Interrupt Status Register (NMISR) Address(es): ICU.NMISR 0008 7580h VBATS LVD1S IWDTS — — WDTST OSTST NMIST Value after reset: Symbol Bit Name Description NMIST NMI Status Flag 0: NMI pin interrupt is not requested 1: NMI pin interrupt is requested OSTST Oscillation Stop Detection...
Page 281 RX23W Group 15. Interrupt Controller (ICUb) WDTST Flag (WDT Underflow/Refresh Error Status Flag) This flag indicates the WDT underflow/refresh error interrupt request. The WDTST flag is read-only, and cleared by the NMICLR.WDTCLR bit. [Setting condition]  When the WDT underflow/refresh error interrupt is generated [Clearing condition] ...
Page 282: Non-Maskable Interrupt Enable Register (Nmier)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.12 Non-Maskable Interrupt Enable Register (NMIER) Address(es): ICU.NMIER 0008 7581h VBATE LVD1E IWDTE WDTE — — OSTEN NMIEN Value after reset: Symbol Bit Name Description NMIEN NMI Pin Interrupt Enable 0: NMI pin interrupt is disabled R/(W) 1: NMI pin interrupt is enabled OSTEN...
Page 283 RX23W Group 15. Interrupt Controller (ICUb) VBATEN Bit (VBATT Voltage Monitoring Interrupt Enable) This bit enables the VBATT voltage monitoring interrupt. A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled. Writing 0 to this bit is disabled. R01UH0823EJ0100 Rev.1.00 Page 283 of 1823 Jul 31, 2019...
Page 284: Non-Maskable Interrupt Status Clear Register (Nmiclr)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.13 Non-Maskable Interrupt Status Clear Register (NMICLR) Address(es): ICU.NMICLR 0008 7582h VBATC LVD1C IWDTC WDTCL OSTCL NMICL — — Value after reset: Symbol Bit Name Description NMICLR NMI Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.NMIST flag. R/(W) Writing 0 to this bit has no effect.
Page 285: Nmi Pin Interrupt Control Register (Nmicr)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.14 NMI Pin Interrupt Control Register (NMICR) Address(es): ICU.NMICR 0008 7583h — — — — NMIMD — — — Value after reset: Symbol Bit Name Description b2 to b0 — Reserved These bits are read as 0. The write value should be 0. NMIMD NMI Detection Set 0: Falling edge...
Page 286: Nmi Pin Digital Filter Setting Register (Nmifltc)
RX23W Group 15. Interrupt Controller (ICUb) 15.2.16 NMI Pin Digital Filter Setting Register (NMIFLTC) Address(es): ICU.NMIFLTC 0008 7594h — — — — — — NFCLKSEL[1:0] Value after reset: Symbol Bit Name Description b1, b0 NFCLKSEL[1:0] NMI Digital Filter Sampling b1 b0 0 0: PCLK Clock 0 1: PCLK/8...
Page 287: Vector Table
RX23W Group 15. Interrupt Controller (ICUb) 15.3 Vector Table There are two types of interrupts detected by the interrupt controller: maskable interrupts and non-maskable interrupts. When the CPU accepts an interrupt or non-maskable interrupt, it acquires a 4-byte vector address from the vector table. 15.3.1 Interrupt Vector Table The interrupt vector table is placed in the 1024-byte range (4 bytes ×...
Page 288 RX23W Group 15. Interrupt Controller (ICUb) Table 15.3 Interrupt Vector Table (1/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER — For an unconditional trap 0000h — — — — — For an unconditional trap 0004h —...
Page 289 RX23W Group 15. Interrupt Controller (ICUb) Table 15.3 Interrupt Vector Table (2/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER RSPI0 SPEI0 00B0h Level IER05.IEN4 IPR044 —  SPRI0 00B4h Edge  ...
Page 290 RX23W Group 15. Interrupt Controller (ICUb) Table 15.3 Interrupt Vector Table (3/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER VBATT VBTLVDI 016Ch Edge IER0B.IEN3 IPR091 —   0170h Edge  ...
Page 291 RX23W Group 15. Interrupt Controller (ICUb) Table 15.3 Interrupt Vector Table (4/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER MTU4 TGIA4 0218h Edge IER10.IEN6 IPR134 DTCER134    TGIB4 021Ch Edge ...
Page 292 RX23W Group 15. Interrupt Controller (ICUb) Table 15.3 Interrupt Vector Table (5/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER TMR2 CMIA2 02D0h Edge IER16.IEN4 IPR180 DTCER180   CMIB2 02D4h Edge ...
Page 293: Fast Interrupt Vector Table
RX23W Group 15. Interrupt Controller (ICUb) Table 15.3 Interrupt Vector Table (6/6) Source of Interrupt Vector Form of Request Vector Address Interrupt Generation Name No.* Offset Detection DTCER 0388h Level IER1C.IEN2 IPR226 —  038Ch Edge    IER1C.IEN3 DTCER227 0390h Edge...
Page 294: Interrupt Operation
RX23W Group 15. Interrupt Controller (ICUb) 15.4 Interrupt Operation The interrupt controller performs the following processing.  Detecting interrupts  Enabling and disabling interrupts  Selecting interrupt request destinations (CPU interrupt, DTC trigger, or DMAC trigger)  Determining priority 15.4.1 Detecting Interrupts Interrupt requests are detected in either of two ways: the detection of edges of the interrupt signal or the detection of a level of the interrupt signal.
Page 295 RX23W Group 15. Interrupt Controller (ICUb) Figure 15.3 to Figure 15.6 show the interrupt signals of the interrupt controller. Note that the timings of the interrupts with interrupt vector numbers 64 to 95 are different from those of other interrupts. For the IRQ pin interrupts with interrupt vector numbers 64 to 79, “internal delay + 2 PCLK cycles”...
Page 296: Operation Of Status Flags For Level-Detected Interrupts
RX23W Group 15. Interrupt Controller (ICUb) 15.4.1.2 Operation of Status Flags for Level-Detected Interrupts Figure 15.6 shows the operation of the interrupt status flag (IR flag) in IRn (n = interrupt vector number) in the case of level detection of an interrupt from a peripheral module or an external pin. The IR flag in IRn remains set to 1 as long as the interrupt signal is asserted.
Page 297: Enabling And Disabling Interrupt Sources
RX23W Group 15. Interrupt Controller (ICUb) 15.4.2 Enabling and Disabling Interrupt Sources Enabling requests from a given interrupt source requires the following settings. 1. In the case of interrupt requests from peripheral modules, setting the interrupt enable bit for the peripheral module to permit the output of interrupt requests from the source 2.
Page 298: Selecting Interrupt Request Destinations
RX23W Group 15. Interrupt Controller (ICUb) 15.4.3 Selecting Interrupt Request Destinations Possible settings for the request destination of each interrupt are fixed. That is, settings for request destination other than those indicated in Table 15.3, Interrupt Vector Table , are not possible. Do not make an interrupt request destination setting that is not indicated by a “”...
Page 299 RX23W Group 15. Interrupt Controller (ICUb) (3) CPU Interrupt Request If the interrupt request destination is neither the DMAC nor the DTC, the interrupt request is sent to the CPU. Set the IERm.IENj bit (m = 02h to 1Fh, j = 0 to 7) to 1 while neither the DMAC trigger settings nor the DTC trigger settings described above are in place.
Page 300: Determining Priority
RX23W Group 15. Interrupt Controller (ICUb) 15.4.4 Determining Priority Interrupt priority is determined for each interrupt request destination. The priority for each interrupt request destination is determined as follows. (1) Determining Priority when the CPU is the Request Destination of the Interrupt A source selected for the fast interrupt has the highest priority.
Page 301: Digital Filter
RX23W Group 15. Interrupt Controller (ICUb) 15.4.7 Digital Filter The digital filter function is provided for the external interrupt request IRQi pins (i = 0, 1, and 4 to 7) and NMI pin interrupt. The digital filter samples input signals at the filter sampling clock (PCLK) and removes the pulses of which length is less than three sampling cycles.
Page 302: Non-Maskable Interrupt Operation
RX23W Group 15. Interrupt Controller (ICUb) 15.5 Non-maskable Interrupt Operation There are six types of non-maskable interrupt: the NMI pin interrupt, oscillation stop detection interrupt, WDT underflow/refresh error, IWDT underflow/refresh error, voltage monitoring 1 interrupt, and VBATT voltage monitoring interrupt. Non-maskable interrupts are only usable as interrupts for the CPU; that is, they are not capable of DTC or DMAC trigger.
Page 303: Return From Power-Down States
RX23W Group 15. Interrupt Controller (ICUb) 15.6 Return from Power-Down States The interrupt sources that can be used to return operation from sleep mode, deep sleep mode, or software standby mode are listed in Table 15.3, Interrupt Vector Table . For details, refer to section 11, Low Power Consumption .
Page 304: Usage Note
RX23W Group 15. Interrupt Controller (ICUb) 15.7 Usage Note 15.7.1 Note on WAIT Instruction Used with Non-Maskable Interrupt Before executing the WAIT instruction, check to see that all the status flags in NMISR are 0. R01UH0823EJ0100 Rev.1.00 Page 304 of 1823 Jul 31, 2019...
Page 305: Buses
RX23W Group 16. Buses Buses 16.1 Overview Table 16.1 lists the bus specifications, Figure 16.1 shows the bus configuration, and Table 16.2 lists the addresses assigned for each bus. Table 16.1 Bus Specifications Bus Type Description  Connected to the CPU (for instructions) CPU bus Instruction bus ...
Page 306 RX23W Group 16. Buses ICLK synchronization Instruction bus Operand bus Memory bus 1 Memory bus 2 Bus error monitoring section DTC/ DMAC(m) Internal main bus 1 Internal main bus 2 Internal peripheral bus 1 Internal peripheral Internal peripheral Internal peripheral buses 2 and 3 bus 6 bus 4...
Page 307: Description Of Buses
RX23W Group 16. Buses 16.2 Description of Buses 16.2.1 CPU Buses The CPU buses consist of the instruction and operand buses, which are connected to internal main bus 1. As the names suggest, the instruction bus is used to fetch instructions for the CPU, while the operand bus is used for operand access. The instruction bus is 64 bits while the operand bus is 32 bits.
Page 308: Internal Peripheral Buses
RX23W Group 16. Buses Table 16.3 Order of Priority for Bus Masters Priority Internal main buses Bus Master High DMAC Note: The above applies when the priority order of the buses is fixed. The priority order of internal main bus 1 and another bus (internal main bus 2) can be toggled by the bus priority control register (BUSPRI) (round-robin method).
Page 309: Write Buffer Function (Internal Peripheral Bus)
RX23W Group 16. Buses Priority order fixed: Internal main bus 1 (R11) (R11) (R11) (R13) (R13) Internal main bus 2 Priority order toggled: Internal main bus 1 (R11) (R12) (R22) Internal main bus 2 (1), (2) : The priority order does not change because the priority of the accepted request is low. Request issued;...
Page 310: Parallel Operation
RX23W Group 16. Buses 16.2.6 Parallel Operation Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For example, if the CPU is fetching an instruction from ROM and an operand from RAM, the DMAC is able to handle transfer between a peripheral bus and the peripheral bus at the same time.
Page 311: Register Descriptions
RX23W Group 16. Buses 16.3 Register Descriptions 16.3.1 Bus Error Status Clear Register (BERCLR) Address(es): 0008 1300h STSCL — — — — — — — Value after reset: Symbol Bit Name Description STSCLR Status Clear 0: Invalid (W)* 1: Bus error status register cleared b7 to b1 —...
Page 312: Bus Error Status Register 1 (Bersr1)
RX23W Group 16. Buses 16.3.3 Bus Error Status Register 1 (BERSR1) Address(es): 0008 1308h — MST[2:0] — — Value after reset: Symbol Bit Name Description Illegal Address Access 0: Illegal address access not made 1: Illegal address access made Timeout 0: Timeout not generated 1: Timeout generated b3, b2...
Page 313: Bus Priority Control Register (Buspri)
RX23W Group 16. Buses 16.3.5 Bus Priority Control Register (BUSPRI) Address(es): 0008 1310h — — — — BPFB[1:0] BPHB[1:0] BPGB[1:0] BPIB[1:0] BPRO[1:0] BPRA[1:0] Value after reset: Symbol Bit Name Description b1, b0 BPRA[1:0] Memory Bus 1 (RAM) Priority R(/W) b1 b0 0 0: The order of priority is fixed.
Page 314 RX23W Group 16. Buses When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted. BPGB[1:0] Bits (Internal Peripheral Bus 2 and 3 Priority Control) These bits specify the priority order for internal peripheral buses 2 and 3. When the priority order is fixed, internal main bus 2 has priority over internal main bus 1.
Page 315: Bus Error Monitoring Section
RX23W Group 16. Buses 16.4 Bus Error Monitoring Section The bus error monitoring section monitors the individual areas for bus errors, and when a bus error occurs, the error is indicated to the bus master. 16.4.1 Types of Bus Error There are two types of bus error: illegal address access and timeout.
Page 316: Operations When A Bus Error Occurs
RX23W Group 16. Buses 16.4.2 Operations When a Bus Error Occurs When a bus error occurs, the error is indicated to the CPU. Operation is not guaranteed when a bus error occurs.  Bus error indication to the CPU An interrupt is generated. The IERn register in the ICU can specify whether to generate an interrupt in the case of a bus error.
Page 317: Interrupt
RX23W Group 16. Buses 16.5 Interrupt 16.5.1 Interrupt Source An illegal address access error or detection of a timeout leads to a bus error signal for the interrupt controller. Table 16.6 Interrupt Source Name Interrupt Source DTC Activation DMAC Activation BUSERR Illegal address access error or timeout Not possible...
Page 318: Memory-Protection Unit (Mpu)
RX23W Group 17. Memory-Protection Unit (MPU) Memory-Protection Unit (MPU) 17.1 Overview The RXv2 CPU incorporates a memory-protection unit that checks the addresses of CPU access to the overall address space (0000 0000h to FFFF FFFFh). Access-control information can be set for up to eight regions, and permission for access to each region is in accord with this information.
Page 319 RX23W Group 17. Memory-Protection Unit (MPU) A4 A0 CPU instruction address A4 A0 CPU operand access address Processor mode Access control Background access-control register Start page number register End page number register Region 0 Start page number End page number Access control Region 7 Region 0...
Page 320: Types Of Access Control
RX23W Group 17. Memory-Protection Unit (MPU) 17.1.1 Types of Access Control There are three types of access control information: permission for instruction execution, permission to read operands, and permission to write operands. Violations of these types of access control are only detected when programs are running in user mode.
Page 321: Register Descriptions
RX23W Group 17. Memory-Protection Unit (MPU) 17.2 Register Descriptions 17.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7) Address(es): RSPAGE0 0008 6400h, RSPAGE1 0008 6408h, RSPAGE2 0008 6410h, RSPAGE3 0008 6418h, RSPAGE4 0008 6420h, RSPAGE5 0008 6428h, RSPAGE6 0008 6430h, RSPAGE7 0008 6438h RSPN[27:0] Value after reset: RSPN[27:0]...
Page 322: Region-N End Page Number Register (Repagen) (N = 0 To 7)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7) Address(es): REPAGE0 0008 6404h, REPAGE1 0008 640Ch, REPAGE2 0008 6414h, REPAGE3 0008 641Ch, REPAGE4 0008 6424h, REPAGE5 0008 642Ch, REPAGE6 0008 6434h, REPAGE7 0008 643Ch REPN[27:0] Value after reset: REPN[27:0]...
Page 323: Memory-Protection Enable Register (Mpen)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.3 Memory-Protection Enable Register (MPEN) Address(es): 0008 6500h — — — — — — — — — — — — — — — — Value after reset: — — — — — — — —...
Page 324: Background Access Control Register (Mpbac)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.4 Background Access Control Register (MPBAC) Address(es): 0008 6504h — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 325: Memory-Protection Error Status-Clearing Register (Mpeclr)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.5 Memory-Protection Error Status-Clearing Register (MPECLR) Address(es): 0008 6508h — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 326: Memory-Protection Error Status Register (Mpests)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.6 Memory-Protection Error Status Register (MPESTS) Address(es): 0008 650Ch — — — — — — — — — — — — — — — — Value after reset: — — — — — — —...
Page 327: Data Memory-Protection Error Address Register (Mpdea)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.7 Data Memory-Protection Error Address Register (MPDEA) Address(es): 0008 6514h DEA[31:0] Value after reset: DEA[31:0] Value after reset: x: Undefined Symbol Bit Name Function b31 to b0 DEA[31:0] Data Memory-Protection Error Address Data memory-protection error address DEA[31:0] Bits (Data Memory-Protection Error Address) These bits retain the address for which operand access generated a memory-protection error.
Page 328: Region Search Operation Register (Mpops)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.9 Region Search Operation Register (MPOPS) Address(es): 0008 6524h — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Function Region Search Operation [Reading] Activation 0: Fixed value for reading...
Page 329: Instruction-Hit Region Register (Mhiti)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.11 Instruction-Hit Region Register (MHITI) Address(es): 0008 6528h — — — — — — — — HITI[7:0] Value after reset: — — — — — — — — — — — — UHACI[2:0] — Value after reset: Symbol Bit Name...
Page 330 RX23W Group 17. Memory-Protection Unit (MPU) UHACI[2:0] Bits (Instruction-Hit Region Access Control Bits in User Mode) These bits hold the user-mode access control bits (REPAGEn.UAC[2:0]) for the region where the instruction memory- protection error was generated. If the error was generated in an overlap between regions, the value stored here is the logical OR of the user-mode access control bits for the corresponding regions (including the background region).
Page 331: Data-Hit Region Register (Mhitd)
RX23W Group 17. Memory-Protection Unit (MPU) 17.2.12 Data-Hit Region Register (MHITD) Address(es): 0008 652Ch — — — — — — — — HITD[7:0] Value after reset — — — — — — — — — — — — UHACD[2:0] — Value after reset Symbol Bit Name...
Page 332 RX23W Group 17. Memory-Protection Unit (MPU) HITD[7:0] Bits (Data-Hit Region) These bits indicate the region where a data memory-protection error was generated or the region that produced a hit in a region search. These bits are set to 0000 0000b for a data memory-protection error generated in the background region. Note: When access to a register of memory protection unit in user mode generates a data memory-protection error, the value in this register is cleared to 0000 0000h.
Page 333: Functions
RX23W Group 17. Memory-Protection Unit (MPU) 17.3 Functions 17.3.1 Memory Protection Memory protection means monitoring, in accord with the access-control information that has been set for the individual access-control regions and the background region, whether or not access by programs running in user mode violates the access-control settings.
Page 334: Flow For Determination Of Access By The Memory-Protection Function
RX23W Group 17. Memory-Protection Unit (MPU) 17.3.4 Flow for Determination of Access by the Memory-Protection Function Figure 17.2 shows the flow of determination in the case of data access and Figure 17.3 shows the flow of determination in the case of instruction access. Data access by the CPU Processor mode? Supervisor mode...
Page 335 RX23W Group 17. Memory-Protection Unit (MPU) Instruction access by the CPU Processor mode? Supervisor mode Permit instruction access User mode Is memory protection enabled? Permit instruction access Is access to an access- control region? Determination in accord with Determination in accord with Access prohibited Access prohibited the access-control information...
Page 336: Procedures For Using Memory Protection
RX23W Group 17. Memory-Protection Unit (MPU) 17.4 Procedures for Using Memory Protection 17.4.1 Setting Access-Control Information Access-control information for the various regions is set in supervisor mode. Settings for up to eight access-control regions are made in the region-n start page number registers (RSPAGEn) and region-n end page number registers (REPAGEn), where n = 0 to 7.
Page 337 RX23W Group 17. Memory-Protection Unit (MPU) When a data memory-protection error is generated Access-exception processing by the CPU saves the address of the instruction that led to the memory-protection error on the stack. Furthermore, the address of the operand for which access led to a memory-protection error is stored in the data memory-protection error address register (MPDEA) and the region information for the region where the memory- protection error was generated is stored in the data-hit region register (MHITD).
Page 338: Dma Controller (Dmaca)
RX23W Group 18. DMA Controller (DMACA) DMA Controller (DMACA) This MCU incorporates a 4-channel direct memory access controller (DMAC). The DMAC module performs data transfers without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. 18.1 Overview Table 18.1 lists the specifications of the DMAC, and Figure 18.1 shows a block diagram of the DMAC.
Page 339 RX23W Group 18. DMA Controller (DMACA) DMAC Activation control DMAC registers DMAC channels (CH0 to CH3) DMSAR DMA start transfer request DMDAR request DMCRA arbitration DMCRB DMOFR DMTMD Interrupt DMAMD controller DMSTS DMCNT DMAC response Interrupt request Register control DMAC response control DMAC core Source address...
Page 340: Register Descriptions
RX23W Group 18. DMA Controller (DMACA) 18.2 Register Descriptions 18.2.1 DMA Source Address Register (DMSAR) Address(es): DMAC0.DMSAR 0008 2000h, DMAC1.DMSAR 0008 2040h, DMAC2.DMSAR 0008 2080h, DMAC3.DMSAR 0008 20C0h Value after reset: Value after reset: Description Setting Range b31 to b0 Specifies the transfer source start address.
Page 341: Dma Transfer Count Register (Dmcra)
RX23W Group 18. DMA Controller (DMACA) 18.2.3 DMA Transfer Count Register (DMCRA) Address(es): DMAC0.DMCRA 0008 2008h, DMAC1.DMCRA 0008 2048h, DMAC2.DMCRA 0008 2088h, DMAC3.DMCRA 0008 20C8h  Normal transfer mode DMCRAH — — — — — — Value after reset: DMCRAL Value after reset: ...
Page 342 RX23W Group 18. DMA Controller (DMACA) (2) Repeat Transfer Mode (MD[1:0] Bits in DMACm.DMTMD = 01b) DMCRAH specifies the repeat size and DMCRAL functions as a 10-bit transfer counter. The number of transfer operations is one when the setting is 001h, 1023 when it is 3FFh, and 1024 when it is 000h. In repeat transfer mode, a value in the range of 000h to 3FFh (1 to 1024) can be set for DMCRAH and DMCRAL.
Page 343: Dma Block Transfer Count Register (Dmcrb)
RX23W Group 18. DMA Controller (DMACA) 18.2.4 DMA Block Transfer Count Register (DMCRB) Address(es): DMAC0.DMCRB 0008 200Ch, DMAC1.DMCRB 0008 204Ch, DMAC2.DMCRB 0008 208Ch, DMAC3.DMCRB 0008 20CCh — — — — — — Value after reset: Description Setting Range b9 to b0 Specifies the number of block transfer operations 001h to 3FFh (1 to 1023) or repeat transfer operations.
Page 344: Dma Transfer Mode Register (Dmtmd)
RX23W Group 18. DMA Controller (DMACA) 18.2.5 DMA Transfer Mode Register (DMTMD) Address(es): DMAC0.DMTMD 0008 2010h, DMAC1.DMTMD 0008 2050h, DMAC2.DMTMD 0008 2090h, DMAC3.DMTMD 0008 20D0h MD[1:0] DTS[1:0] — — SZ[1:0] — — — — — — DCTG[1:0] Value after reset: Symbol Bit Name Description...
Page 345: Dma Interrupt Setting Register (Dmint)
RX23W Group 18. DMA Controller (DMACA) 18.2.6 DMA Interrupt Setting Register (DMINT) Address(es): DMAC0.DMINT 0008 2013h, DMAC1.DMINT 0008 2053h, DMAC2.DMINT 0008 2093h, DMAC3.DMINT 0008 20D3h — — — DTIE ESIE RPTIE SARIE DARIE Value after reset: Symbol Bit Name Description DARIE Destination Address 0: Disables an interrupt request for an extended repeat area overflow on...
Page 346 RX23W Group 18. DMA Controller (DMACA) RPTIE Bit (Repeat Size End Interrupt Enable) When this bit is set to 1 in repeat transfer mode, the DTE bit in DMCNT is cleared to 0 after completion of a 1-repeat size data transfer. At the same time, the ESIF flag in DMSTS is set to 1 to indicate that the repeat size end interrupt request has been generated.
Page 347: Dma Address Mode Register (Dmamd)
RX23W Group 18. DMA Controller (DMACA) 18.2.7 DMA Address Mode Register (DMAMD) Address(es): DMAC0.DMAMD 0008 2014h, DMAC1.DMAMD 0008 2054h, DMAC2.DMAMD 0008 2094h, DMAC3.DMAMD 0008 20D4h SM[1:0] — SARA[4:0] DM[1:0] — DARA[4:0] Value after reset: Symbol Bit Name Description b4 to b0 DARA[4:0] Destination Address Extended Specifies the extended repeat area on the destination address.
Page 348 RX23W Group 18. DMA Controller (DMACA) SARA[4:0] Bits (Source Address Extended Repeat Area) These bits specify the extended repeat area on the source address. The extended repeat area function is realized by updating the specified lower address bits with the remaining upper address bits fixed. The size of the extended repeat area can be any power of two between 21 (2 bytes) and 217 (128 Mbytes).
Page 349 RX23W Group 18. DMA Controller (DMACA) Table 18.2 SARA[4:0] or DARA[4:0] Settings and Corresponding Repeat Areas SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area 00000b Not specified 00001b 2 bytes specified as extended repeat area by the lower 1 bit of the address 00010b 4 bytes specified as extended repeat area by the lower 2 bits of the address 00011b...
Page 350: Dma Offset Register (Dmofr)
RX23W Group 18. DMA Controller (DMACA) 18.2.8 DMA Offset Register (DMOFR) Address(es): DMAC0.DMOFR 0008 2018h Value after reset: Value after reset: Description Setting Range b31 to b0 Specifies the offset when offset addition is selected 0000 0000h to 00FF FFFFh (0 bytes to (16 M – 1) bytes) as the address update mode for transfer source or FF00 0000h to FFFF FFFFh (–16 Mbytes to –1 byte) destination.
Page 351: Dma Transfer Enable Register (Dmcnt)
RX23W Group 18. DMA Controller (DMACA) 18.2.9 DMA Transfer Enable Register (DMCNT) Address(es): DMAC0.DMCNT 0008 201Ch, DMAC1.DMCNT 0008 205Ch, DMAC2.DMCNT 0008 209Ch, DMAC3.DMCNT 0008 20DCh — — — — — — — Value after reset: Symbol Bit Name Description DMA Transfer Enable 0: Disables DMA transfer.
Page 352: Dma Software Start Register (Dmreq)
RX23W Group 18. DMA Controller (DMACA) 18.2.10 DMA Software Start Register (DMREQ) Address(es): DMAC0.DMREQ 0008 201Dh, DMAC1.DMREQ 0008 205Dh, DMAC2.DMREQ 0008 209Dh, DMAC3.DMREQ 0008 20DDh SWRE — — — CLRS — — — Value after reset: Symbol Bit Name Description SWREQ DMA Software Start 0: DMA transfer is not requested.
Page 353: Dma Status Register (Dmsts)
RX23W Group 18. DMA Controller (DMACA) 18.2.11 DMA Status Register (DMSTS) Address(es): DMAC0.DMSTS 0008 201Eh, DMAC1.DMSTS 0008 205Eh, DMAC2.DMSTS 0008 209Eh, DMAC3.DMSTS 0008 20DEh — — DTIF — — — ESIF Value after reset: Symbol Bit Name Description ESIF Transfer Escape End Interrupt 0: A transfer escape end interrupt has not been generated.
Page 354 RX23W Group 18. DMA Controller (DMACA) DTIF Flag (Transfer End Interrupt Flag) This flag indicates that the transfer end interrupt has been generated. [Setting conditions]  When the specified number of unit-transfers are completed in normal transfer mode (the value of DMCRAL becoming 0 on completion of transfer) ...
Page 355: Dma Activation Source Flag Control Register (Dmcsl)
RX23W Group 18. DMA Controller (DMACA) 18.2.12 DMA Activation Source Flag Control Register (DMCSL) Address(es): DMAC0.DMCSL 0008 201Fh, DMAC1.DMCSL 0008 205Fh, DMAC2.DMCSL 0008 209Fh, DMAC3.DMCSL 0008 20DFh — — — — — — — DISEL Value after reset: Symbol Bit Name Description DISEL Interrupt Select...
Page 356: Dma Module Activation Register (Dmast)
RX23W Group 18. DMA Controller (DMACA) 18.2.13 DMA Module Activation Register (DMAST) Address(es): 0008 2200h — — — — — — — DMST Value after reset: Symbol Bit Name Description DMST DMAC Operation Enable 0: DMAC activation is disabled. 1: DMAC activation is enabled. b7 to b1 —...
Page 357: Operation
RX23W Group 18. DMA Controller (DMACA) 18.3 Operation 18.3.1 Transfer Mode (1) Normal Transfer Mode In normal transfer mode, one data is transferred by one transfer request. A maximum of 65535 can be set as the number of transfer operations using the DMCRAL of DMACm. When these bits are set to 0000h, no specific number of transfer operations is set;...
Page 358 RX23W Group 18. DMA Controller (DMACA) (2) Repeat Transfer Mode In repeat transfer mode, one data is transferred by one transfer request. A maximum of 1K data can be set as a total repeat transfer size using DMCRA of the DMACm. A maximum of 1K can be set as the number of repeat transfer operations using DMCRB of the DMACm;...
Page 359 RX23W Group 18. DMA Controller (DMACA) Transfer source data area Transfer destination data area (Specified as a repeat area) DMSAR DMDAR Data 1 Data 1 Data 2 Transfer Data 2 Data 3 Data 3 Data 4 Data 4 Data 1 Data 2 Data 3 Data 4...
Page 360 RX23W Group 18. DMA Controller (DMACA) (3) Block Transfer Mode In block transfer mode, a single block data is transferred by one transfer request. A maximum of 1K data can be set as a total block transfer size using DMCRA of the DMACm. A maximum of 1K can be set as the number of block transfer operations using DMCRB of the DMACm;...
Page 361: Extended Repeat Area Function
RX23W Group 18. DMA Controller (DMACA) 18.3.2 Extended Repeat Area Function The DMAC supports a function to specify the extended repeat areas on the transfer source and destination addresses. With the extended repeat areas set, the address registers repeatedly indicate the addresses of the specified extended repeat areas.
Page 362 RX23W Group 18. DMA Controller (DMACA) When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary.
Page 363: Address Update Function Using Offset
RX23W Group 18. DMA Controller (DMACA) 18.3.3 Address Update Function Using Offset The source and destination addresses can be updated by fixing, increment, decrement, or offset addition. When the offset addition is selected, the offset specified by the DMA offset register (DMOFR of DMAC0) is added to the address every time the DMAC performs one data transfer.
Page 364 RX23W Group 18. DMA Controller (DMACA) (1) Basic Transfer Using Offset Addition Figure 18.7 shows an example of address updating using offset addition. Transfer Address B1 Data 1 Address A1 Data 1 Address B2 = address B1 + 4 Data 2 Data 3 Address B3 = address B2 + 4 Offset value...
Page 365 RX23W Group 18. DMA Controller (DMACA) (2) Example of XY Conversion Using Offset Addition Figure 18.8 shows the XY conversion using offset addition in repeat transfer mode. Settings are as follows:  DMAC0.DMAMD: Transfer source address update mode: Offset addition ...
Page 366 RX23W Group 18. DMA Controller (DMACA) Figure 18.9 shows a flowchart of the XY conversion. Start Set the address, repeat size, and number of repeat operations. Set repeat transfer mode. Enable repeat size end interrupts. Write 1 to the DTE bit in DMAC0.DMCNT. Receive a transfer request.
Page 367: Activation Sources
RX23W Group 18. DMA Controller (DMACA) 18.3.4 Activation Sources Software, the interrupt requests from the peripheral modules, and the external interrupt requests can be specified as the DMAC activation sources. Setting the DCTG[1:0] bits in DMTMD of DMACm selects the activation source. (1) DMAC Activation by Software Setting the DCTG[1:0] bits in DMTMD of DMACm to 00b enables the DMAC activation by software.
Page 368: Operation Timing
RX23W Group 18. DMA Controller (DMACA) 18.3.5 Operation Timing Figure 18.10 and Figure 18.11 show DMAC operation timing examples. System clock IRn in the ICU DMAC activation request DMAC access Data transfer Figure 18.10 DMAC Operation Timing Example (1) (DMA Activation by Interrupt from Peripheral Module/ External Interrupt Input Pin, Normal Transfer Mode, Repeat Transfer Mode) System clock IRn in the ICU...
Page 369: Dmac Execution Cycles
RX23W Group 18. DMA Controller (DMACA) 18.3.6 DMAC Execution Cycles Table 18.7 lists execution cycles in one DMAC data transfer operation. Table 18.7 DMAC Execution Cycles Transfer Mode Data Transfer (Read) Data Transfer (Write) Normal Cr+1 Repeat Cr+1 Block* P × Cr P ×...
Page 370: Activating The Dmac
RX23W Group 18. DMA Controller (DMACA) 18.3.7 Activating the DMAC Figure 18.12 shows the register setting procedure. For activation other than by software Start of initial settings Clear the interrupt enable bit (ICU.IERn.IENj) as an activation source to 0, then perform the settings below. To use peripheral function Set the peripheral module as a DMACm request Set the control register for the peripheral function without...
Page 371: Starting Dma Transfer
RX23W Group 18. DMA Controller (DMACA) 18.3.8 Starting DMA Transfer Setting the DTE bit in DMCNT of DMACm to 1 (DMA transfer enabled) and setting the DMST bit in DMAST to 1 (DMAC start enabled) enable DMA transfer of channel m (m = 0 to 3). Another activation request cannot be accepted during the transfer of other DMAC channel or DTC.
Page 372: Channel Priority
RX23W Group 18. DMA Controller (DMACA) (6) DMA Active Flag (DMACm.DMSTS.ACT) The ACT bit in DMSTS of DMACm indicates whether the DMACm is in the idle or active state. This flag is set to 1 when the DMAC starts data transfer, and is cleared to 0 when data transfer in response to one transfer request is completed.
Page 373: Ending Dma Transfer
RX23W Group 18. DMA Controller (DMACA) 18.4 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the DTE bit in DMCNT and the ACT flag in DMSTS of DMACm are changed from 1 to 0, indicating that DMA transfer has ended. 18.4.1 Transfer End by Completion of Specified Total Number of Transfer Operations (1) In Normal Transfer Mode (DMACm.DMTMD.MD[1:0] = 00b)
Page 374: Transfer End By Interrupt On Extended Repeat Area Overflow
RX23W Group 18. DMA Controller (DMACA) 18.4.3 Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DMINT of DMACm is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMCNT of DMACm is cleared to 0, and the ESIF flag in DMSTS of DMACm is set to 1.
Page 375: Interrupts
RX23W Group 18. DMA Controller (DMACA) 18.5 Interrupts Each DMAC channel can output an interrupt request to the CPU or the DTC after transfer in response to one request is completed. When the transfer destination is the on-chip peripheral bus, an interrupt request is generated upon completion of data write to the write buffer not to the actual transfer destination.
Page 376: Event Link Function
RX23W Group 18. DMA Controller (DMACA) Specifically, the different procedures are used for canceling an interrupt to restart DMA transfer in the following two cases: (1) discontinuing or terminating DMA transfer and (2) continuing DMA transfer. (1) When Discontinuing or Terminating DMA Transfer Write 0 to the DTIF bit in DMSTS of DMACm to clear a transfer end interrupt, and to the ESIF bit in DMSTS of DMACm to clear a repeat size interrupt and an extended repeat area overflow interrupt.
Page 377: Low Power Consumption Function
RX23W Group 18. DMA Controller (DMACA) 18.7 Low Power Consumption Function Before transition to the module stop state or software standby mode, clear the DMAST.DMST bit to 0 (DMAC activation is disabled), and then perform the following. (1) Module Stop Function Writing 1 to the MSTPA28 bit (transition to the module-stop state) in MSTPCRA enables the module-stop function of the DMAC.
Page 378: Usage Notes
RX23W Group 18. DMA Controller (DMACA) 18.8 Usage Notes 18.8.1 DMA Transfer to Peripheral Modules In DMA transfer to a peripheral module, the ACT bit in DMSTS of DMACm may be cleared to 0 (DMAC transfer suspended) during the period from the beginning of the final data write to the end of the peripheral bus access. 18.8.2 Access to the Registers during DMA Transfer The DMSAR, DMDAR, DMCRA, DMCRB, DMTMD, DMINT, DMAMD, DMOFR, and DMCSL registers of...
Page 379: Data Transfer Controller (Dtca)
RX23W Group 19. Data Transfer Controller (DTCa) Data Transfer Controller (DTCa) This MCU incorporates a data transfer controller (DTC). The DTC is triggered by an interrupt request to perform data transfers. 19.1 Overview Table 19.1 lists the specifications of the DTC, and Figure 19.1 shows a block diagram of the DTC. Table 19.1 DTC Specifications Item...
Page 380 RX23W Group 19. Data Transfer Controller (DTCa) Register Vector number control Interrupt controller Activation Transfer request control DTC response Bus interface DTCCR DTCVBR response control DTCADMOD DTCST DTCSTS Internal peripheral bus 1 Internal main bus 2 Internal main bus 1 Internal Memory bus 2 Memory bus 1...
Page 381: Register Descriptions
RX23W Group 19. Data Transfer Controller (DTCa) 19.2 Register Descriptions Registers MRA, MRB, SAR, DAR, CRA, and CRB are DTC internal registers, which cannot be directly accessed from the CPU. Values to be set in these DTC internal registers are placed in the RAM area as transfer information. When accepting a transfer request, the DTC reads the transfer information from the RAM area and sets it in the internal registers.
Page 382: Dtc Mode Register B (Mrb)
RX23W Group 19. Data Transfer Controller (DTCa) 19.2.2 DTC Mode Register B (MRB) Address(es): (inaccessible directly from the CPU) CHNE CHNS DISEL DM[1:0] — — Value after reset: x: Undefined Symbol Bit Name Description b1, b0 — Reserved Set these bits to 0. —...
Page 383: Dtc Transfer Source Register (Sar)
RX23W Group 19. Data Transfer Controller (DTCa) 19.2.3 DTC Transfer Source Register (SAR) Address(es): (inaccessible directly from the CPU) Value after reset: Value after reset: x: Undefined SAR register is used to set the transfer source start address. In full-address mode, 32 bits are valid. In short-address mode, lower 24 bits are valid and upper 8 bits (b31 to b24) are ignored.
Page 384: Dtc Transfer Count Register A (Cra)
RX23W Group 19. Data Transfer Controller (DTCa) 19.2.5 DTC Transfer Count Register A (CRA)  Normal transfer mode Address(es): (inaccessible directly from the CPU) Value after reset: x: Undefined  Repeat transfer mode/block transfer mode Address(es): (inaccessible directly from the CPU) CRAH CRAL Value after reset:...
Page 385: Dtc Transfer Count Register B (Crb)
RX23W Group 19. Data Transfer Controller (DTCa) 19.2.6 DTC Transfer Count Register B (CRB) Address(es): (inaccessible directly from the CPU) Value after reset: x: Undefined CRB register is used to set the block transfer count for block transfer mode and cannot be accessed directly from the CPU.
Page 386: Dtc Vector Base Register (Dtcvbr)
RX23W Group 19. Data Transfer Controller (DTCa) 19.2.8 DTC Vector Base Register (DTCVBR) Address(es): DTC.DTCVBR 0008 2404h Value after reset: Value after reset: The DTCVBR register is used to set the base address for calculating the address to which the DTC vector is allocated. Writing to the upper 4 bits (b31 to b28) is ignored, and the address of this register is extended by the value specified by b27.
Page 387: Dtc Module Start Register (Dtcst)
RX23W Group 19. Data Transfer Controller (DTCa) 19.2.10 DTC Module Start Register (DTCST) Address(es): DTC.DTCST 0008 240Ch — — — — — — — DTCST Value after reset: Symbol Bit Name Description DTCST DTC Module Start 0: DTC module stop 1: DTC module start b7 to b1 —...
Page 388: Dtc Status Register (Dtcsts)
RX23W Group 19. Data Transfer Controller (DTCa) 19.2.11 DTC Status Register (DTCSTS) Address(es): DTC.DTCSTS 0008 240Eh — — — — — — — VECN[7:0] Value after reset: Symbol Bit Name Description b7 to b0 VECN[7:0] DTC Active Vector Number These bits indicate the vector number for the request source when Monitoring Flag data transfer is in progress.
Page 389: Request Sources
RX23W Group 19. Data Transfer Controller (DTCa) 19.3 Request Sources The DTC data transfer is triggered by an interrupt request. Setting the ICU.DTCERn.DTCE bit (n = interrupt vector number) to 1 selects the corresponding interrupt request as a request source for the DTC. For the correspondence between the DTC request sources and the vector addresses, refer to section 15.3.1, Interrupt Vector Table in section 15, Interrupt Controller (ICUb) .
Page 390 RX23W Group 19. Data Transfer Controller (DTCa) DTC vector table Transfer information 0 DTC vector base address Start address of transfer information 0 Start address of transfer information 1 Start address of Transfer information 1 transfer information 2 Start address of transfer information n 4 bytes Transfer information n...
Page 391: Operation
RX23W Group 19. Data Transfer Controller (DTCa) 19.4 Operation The DTC transfers data in accordance with the transfer information. Storage of the transfer information in the RAM area is required before DTC operation. When the DTC accepts a transfer request, it reads the DTC vector corresponding to the vector number. Next, the DTC reads transfer information from the address pointed by the DTC vector, transfers data, and then writes back the transfer information after the data transfer.
Page 392 RX23W Group 19. Data Transfer Controller (DTCa) Start Match and RRS bit = 1 Compare vector numbers. Match? Unmatch or RRS bit = 0 Read DTC vector Next transfer Read transfer information CHNE bit = 1? MD[1:0] bits = 01b? CHNS bit = 0? (Repeat transfer mode?) Last data transfer?
Page 393: Transfer Information Read Skip Function
RX23W Group 19. Data Transfer Controller (DTCa) Table 19.3 Chain Transfer Conditions First Transfer Second Transfer* CHNE CHNS DISEL Transfer CHNE CHNS DISEL Transfer Counter* Counter* Data Transfer — Other than (1 → 0) — — — — Ends after the first transfer —...
Page 394: Transfer Information Write-Back Skip Function
RX23W Group 19. Data Transfer Controller (DTCa) 19.4.2 Transfer Information Write-Back Skip Function When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to “address is fixed” (00b or 01b), a part of transfer information is not written back. This function is performed independently of the setting of short-address mode or full- address mode.
Page 395: Normal Transfer Mode
RX23W Group 19. Data Transfer Controller (DTCa) 19.4.3 Normal Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single transfer request. The transfer count can be set to 1 to 65536. Transfer source addresses and transfer destination addresses can be set to increment, decrement, or fixed independently. This mode enables an interrupt request to the CPU to be generated at the end of specified-count transfer.
Page 396: Repeat Transfer Mode
RX23W Group 19. Data Transfer Controller (DTCa) 19.4.4 Repeat Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single transfer request. Specify either transfer source or transfer destination for the repeat area by the MRB.DTS bit. The transfer count can be set to 1 to 256.
Page 397: Block Transfer Mode
RX23W Group 19. Data Transfer Controller (DTCa) 19.4.5 Block Transfer Mode This mode allows single-block data transfer on a single transfer request. Specify either transfer source or transfer destination for the block area by the MRB.DTS bit. The block size can be set to 1 to 256 bytes, 1 to 256 words, or 1 to 256 longwords.
Page 398: Chain Transfer
RX23W Group 19. Data Transfer Controller (DTCa) 19.4.6 Chain Transfer Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single transfer request. If the MRB.CHNE bit is 1 and the MRB.CHNS bit is 0, an interrupt request to the CPU is not generated when the specified number of data transfers is completed, or while the MRB.DISEL bit is 1 (an interrupt request to the CPU is generated for every data transfer).
Page 399: Operation Timing
RX23W Group 19. Data Transfer Controller (DTCa) 19.4.7 Operation Timing Figure 19.9 to Figure 19.13 show examples of DTC operation timing. System clock ICU.IRn DTC transfer request DTC access Transfer Data Vector read Transfer information read transfer information write n = Vector number Figure 19.9 Example (1) of DTC Operation Timing (Short-Address Mode, Normal Transfer Mode, Repeat Transfer Mode)
Page 400 RX23W Group 19. Data Transfer Controller (DTCa) System clock ICU.IRn DTC transfer request DTC access Data Transfer Data Transfer Transfer Transfer Vector read transfer transfer information read information information information write read write n = Vector number Figure 19.11 Example (3) of DTC Operation Timing (Short-Address Mode, Chain Transfer) System clock ICU.IRn DTC transfer request...
Page 401 RX23W Group 19. Data Transfer Controller (DTCa) System clock ICU.IRn DTC transfer request Read skip enable DTC access Data Transfer Vector read Transfer Transfer Data transfer information write information read transfer information write n = Vector number Note: When request sources (vector numbers) of (1) and (2) are the same and the DTCCR.RRS bit is 1, the transfer information read for request (2) is skipped.
Page 402: Execution Cycles Of The Dtc
RX23W Group 19. Data Transfer Controller (DTCa) 19.4.8 Execution Cycles of the DTC Table 19.8 lists the execution cycles of single data transfer of the DTC. For the order of the execution states, refer to section 19.4.7, Operation Timing . Table 19.8 Execution Cycles of the DTC Data Transfer...
Page 403: Dtc Setting Procedure
RX23W Group 19. Data Transfer Controller (DTCa) 19.5 DTC Setting Procedure Before using the DTC, set the DTC vector base register (DTCVBR). Figure 19.14 shows the procedure to set the DTC. Set the ICU.IERm.IENj bit corresponding to the request source interrupt to 0 and provide the following settings.
Page 404: Examples Of Dtc Usage
RX23W Group 19. Data Transfer Controller (DTCa) 19.6 Examples of DTC Usage 19.6.1 Normal Transfer As an example of DTC usage, its employment in the reception of 128 bytes of data by an SCI is described below. (1) Transfer Information Setting Set the MRA.MD[1:0] bits to 00b (normal transfer mode), the MRA.SZ[1:0] bits to 00b (byte transfer), and the MRA.SM[1:0] bits to 00b (source address is fixed).
Page 405: Chain Transfer When The Counter Is 0
RX23W Group 19. Data Transfer Controller (DTCa) 19.6.2 Chain Transfer When the Counter is 0 The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data transfer information is repeatedly changed in the second data transfer. Repeating this chain transfer enables transfers to be repeated more than 256 times.
Page 406: Interrupt Source
RX23W Group 19. Data Transfer Controller (DTCa) Input circuit Transfer information allocated in the on-chip memory space Input buffer First data transfer Transfer information Chain transfer (counter = 0) Second data transfer Transfer information Upper 8 bits of DAR Figure 19.15 Chain Transfer When the Counter is 0 19.7 Interrupt Source...
Page 407: Low Power Consumption Function
RX23W Group 19. Data Transfer Controller (DTCa) 19.9 Low Power Consumption Function Before making a transition to the module stop state, deep sleep mode, or software standby mode, set the DTCST.DTCST bit to 0 (DTC module stop), and then perform the following. (1) Module Stop Function Writing 1 (transition to the module-stop state is made) to the MSTPCRA.MSTPA28 bit enables the module stop function of the DTC.
Page 408: 19.10 Usage Notes
RX23W Group 19. Data Transfer Controller (DTCa) 19.10 Usage Notes 19.10.1 Start Address of Transfer Information Set multiples of 4 for the start addresses of the transfer information to be specified in the DTC vector table. If any value other than a multiple of 4 is specified, access still proceeds with the lower 2 bits of the address regarded as 00b. 19.10.2 Allocating Transfer Information Allocate transfer information in the memory area according to the endian of the area as shown in Figure 19.16 .
Page 409: Setting The Dtc Transfer Request Enable Register In The Interrupt Controller (Icu.dtcern)
RX23W Group 19. Data Transfer Controller (DTCa) 19.10.3 Setting the DTC Transfer Request Enable Register in the Interrupt Controller (ICU.DTCERn) The DMA request should not be issued by setting the DMAC trigger select register (ICU.DMRSRm (m = DMAC channel number)) to the same vector number that has been specified by setting the ICU.DTCERn.DTCE bit to 1 (the corresponding interrupt source is selected as the DTC trigger).
Page 410: Event Link Controller (Elc)
RX23W Group 20. Event Link Controller (ELC) Event Link Controller (ELC) 20.1 Overview The event link controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals, and interconnects (links) peripheral modules. As a result, peripheral modules can directly perform interlinked operation among them without using software.
Page 411: Register Descriptions
RX23W Group 20. Event Link Controller (ELC) 20.2 Register Descriptions 20.2.1 Event Link Control Register (ELCR) Address(es): ELC.ELCR 0008 B100h ELCON — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 1.
Page 412: Event Link Setting Register N (Elsrn) (N = 1 To 4, 7, 8, 10, 12, 14 To 16, 18 To 29)
RX23W Group 20. Event Link Controller (ELC) 20.2.2 Event Link Setting Register n (ELSRn) (n = 1 to 4, 7, 8, 10, 12, 14 to 16, 18 to 29) Address(es): ELC.ELSR1 0008 B102h, ELC.ELSR2 0008 B103h, ELC.ELSR3 0008 B104h, ELC.ELSR4 0008 B105h, ELC.ELSR7 0008 B108h, ELC.ELSR8 0008 B109h, ELC.ELSR10 0008 B10Bh, ELC.ELSR12 0008 B10Dh, ELC.ELSR14 0008 B10Fh, ELC.ELSR15 0008 B110h, ELC.ELSR16 0008 B111h, ELC.ELSR18 0008 B113h, ELC.ELSR19 0008 B114h, ELC.ELSR20 0008 B115h, ELC.ELSR21 0008 B116h, ELC.ELSR22 0008 B117h, ELC.ELSR23 0008 B118h, ELC.ELSR24 0008 B119h, ELC.ELSR25 0008 B11Ah, ELC.ELSR26 0008 B11Bh,...
Page 413 RX23W Group 20. Event Link Controller (ELC) Table 20.3 Correspondence between Values Set in ELSRn.ELS[7:0] Bits and Event Signals (1/2) ELS[7:0] Bit Value Peripheral Modules Event Signal Set in ELSRn Multifunction timer pulse unit 2 MTU1 compare match 1A MTU1 compare match 1B MTU1 overflow MTU1 underflow MTU2 compare match 2A...
Page 414 RX23W Group 20. Event Link Controller (ELC) Table 20.3 Correspondence between Values Set in ELSRn.ELS[7:0] Bits and Event Signals (2/2) ELS[7:0] Bit Value Peripheral Modules Event Signal Set in ELSRn 12-bit A/D converter S12AD A/D conversion end Voltage detection circuit LVD1 voltage detection DMA controller DMAC0 transfer end...
Page 415: Event Link Option Setting Register A (Elopa)
RX23W Group 20. Event Link Controller (ELC) 20.2.3 Event Link Option Setting Register A (ELOPA) Address(es): ELC.ELOPA 0008 B11Fh MTU3MD[1:0] MTU2MD[1:0] MTU1MD[1:0] — — Value after reset: Symbol Bit Name Description b1, b0 — Reserved These bits are read as 1. The write value should be 1. b3, b2 MTU1MD[1:0] MTU1 Operation Select...
Page 416: Event Link Option Setting Register C (Elopc)
RX23W Group 20. Event Link Controller (ELC) 20.2.5 Event Link Option Setting Register C (ELOPC) Address(es): ELC.ELOPC 0008 B121h — — LPTMD[1:0] CMT1MD[1:0] — — Value after reset: Symbol Bit Name Description b1, b0 — Reserved These bits are read as 1. The write value should be 1. b3, b2 CMT1MD[1:0] CMT1 Operation Select...
Page 417: Port Group Setting Register N (Pgrn) (N = 1, 2)
RX23W Group 20. Event Link Controller (ELC) 20.2.7 Port Group Setting Register n (PGRn) (n = 1, 2) Address(es): ELC.PGR1 0008 B123h, ELC.PGR2 0008 B124h PGR7 PGR6 PGR5 PGR4 PGR3 PGR2 PGR1 PGR0 Value after reset: Symbol Bit Name Description PGR0 Port Group Setting 0 0: Does not specify the port as a member of the port group.
Page 418: Port Group Control Register N (Pgcn) (N = 1, 2)
RX23W Group 20. Event Link Controller (ELC) 20.2.8 Port Group Control Register n (PGCn) (n = 1, 2) Address(es): ELC.PGC1 0008 B125h, ELC.PGC2 0008 B126h PGCO — PGCO[2:0] — PGCI[1:0] Value after reset: Symbol Bit Name Description b1, b0 PGCI[1:0] Event Output Edge Select b1 b0 0 0: Event signal is output upon detection of the rising edge...
Page 419: Port Buffer Register N (Pdbfn) (N = 1, 2)
RX23W Group 20. Event Link Controller (ELC) 20.2.9 Port Buffer Register n (PDBFn) (n = 1, 2) Address(es): ELC.PDBF1 0008 B127h, ELC.PDBF2 0008 B128h PDBF7 PDBF6 PDBF5 PDBF4 PDBF3 PDBF2 PDBF1 PDBF0 Value after reset: Symbol Bit Name Description PDBF0 Port Buffer 0 Specify the data to be transferred to the PODR register when an event signal is input.
Page 420: Event Link Port Setting Register M (Pelm) (M = 0 To 3)
RX23W Group 20. Event Link Controller (ELC) 20.2.10 Event Link Port Setting Register m (PELm) (m = 0 to 3) Address(es): ELC.PEL0 0008 B129h, ELC.PEL1 0008 B12Ah, ELC.PEL2 0008 B12Bh, ELC.PEL3 0008 B12Ch — PSM[1:0] PSP[1:0] PSB[2:0] Value after reset: Symbol Bit Name Description...
Page 421: Event Link Software Event Generation Register (Elsegr)
RX23W Group 20. Event Link Controller (ELC) 20.2.11 Event Link Software Event Generation Register (ELSEGR) Address(es): ELC.ELSEGR 0008 B12Dh — — — — — Value after reset: Symbol Bit Name Description Software Event Generation 0: Normal operation 1: Software event is generated. b5 to b1 —...
Page 422: Operation
RX23W Group 20. Event Link Controller (ELC) 20.3 Operation 20.3.1 Relation between Interrupt Handling and Event Linking The peripheral modules incorporated in the MCU are provided with the interrupt request status flags and the interrupt enable bits to enable/disable these interrupt requests. When an interrupt request is generated in a peripheral module, the corresponding interrupt request status flag becomes 1.
Page 423: Event Linkage
RX23W Group 20. Event Link Controller (ELC) 20.3.2 Event Linkage When events are specified in the ELSRn registers, the corresponding peripheral modules can be operated at generation of the specified events. A single peripheral module can link only with a single event. Set the ELSRn register after completing the initialization of the peripheral module to operate by an event.
Page 424: Operation Of Peripheral Timer Modules When Event Signal Is Input
RX23W Group 20. Event Link Controller (ELC) 20.3.3 Operation of Peripheral Timer Modules When Event Signal is Input For the timer modules, set the ELOPA to ELOPD register to specify the operation for when an event signal is input. (1) Count Start Operation When an event signal is input, the timer starts counting and the count start bit * in each timer control register becomes 1.
Page 425 RX23W Group 20. Event Link Controller (ELC) (2) Event Generation in Single Input Ports A single port that is set as input generates an event signal when the input signal to the corresponding pin changes. The event generation condition is specified using the PELm.PSM[1:0] bits (m = 0 to 3). An example of operation is shown in Figure 20.3 (1) .
Page 426 RX23W Group 20. Event Link Controller (ELC) (5) Input Port Group Operation When Event Signal is Input When an event signal is input to an input port group, the level of the corresponding pins is transferred to the PDBFn register. Values of the bits corresponding to ports that are not specified as members of the input port group do not change. An example of operation is shown in Figure 20.4 .
Page 427 RX23W Group 20. Event Link Controller (ELC) (7) Operation of the PDBFn Registers (a) Input Port Groups When an event signal is input to an input port group, the level of the corresponding pins is transferred to the PDBFn register (n = 1, 2). When another event signal is input to the input port group in this condition, different operations are performed depending on the PGCn.PGCOVE bit setting described as below.
Page 428: Example Of Procedure For Linking Events
RX23W Group 20. Event Link Controller (ELC) (8) Restrictions on Writing to PODR and PDBF Registers When the ELCR.ELCON bit is 1 (ELC function is enabled), write access to the PODR and PDBFn registers (n = 1, 2) becomes disabled at the following conditions. ...
Page 429: Usage Notes
RX23W Group 20. Event Link Controller (ELC) 20.4 Usage Notes 20.4.1 Setting ELSRn Register (1) Setting ELSR8 Register Set this register to 32h (LPT compare match). (2) Setting ELSR18 and ELSR19 Registers Specify an event number from among 63h to 6Ah. Do not set the value other than preceding numbers. (3) Setting ELSR24, ELSR25, ELSR26, and ELSR27 Registers Do not set the DOC data operation condition met signal (6Ah).
Page 430: I/O Ports
RX23W Group 21. I/O Ports I/O Ports 21.1 Overview The I/O ports function as a general I/O port, an I/O pin of a peripheral module, an input pin for an interrupt, or a bus control pin. Some of the pins are also configurable as an I/O pin of a peripheral module or an input pin for an interrupt. All pins function as input pins immediately after a reset, and pin functions are switched by register settings.
Page 431 RX23W Group 21. I/O Ports Table 21.2 Port Functions Port Input Pull-up Open Drain Output Drive Capacity Switching 5-V Tolerant PORT0 P03, P05, P07 — Fixed to normal output —  PORT1 P16, P17     P14, P15 —...
Page 432: I/O Port Configuration
RX23W Group 21. I/O Ports 21.2 I/O Port Configuration Port 0: P03, P05 1: ON 0: OFF PODR Reading the port ASEL bit DA output enable signal Analog output Port 0: P07 1: ON 0: OFF Enable peripheral module output PODR Peripheral module output signal Input signal of peripheral module/interrupt...
Page 433 RX23W Group 21. I/O Ports Port 1: P16, P17 Port J: PJ3 1: ON 0: OFF ODR0, ODR1 Enable peripheral module output PODR Peripheral module output signal Input signal of peripheral module/interrupt Reading the port ISEL bit Port 1: P14, P15 1: ON 0: OFF ODR0, ODR1...
Page 434 RX23W Group 21. I/O Ports Port 2: P21, P22, P25 1: ON Port C: PC0, PC2, PC3, PC5, PC6 0: OFF ODR0, ODR1 Peripheral module output signal PODR Peripheral module output signal Input signal of peripheral module/interrupt Reading the port CTSU channel enable control register Sensor drive pulse Port 2: P26, P27...
Page 435 RX23W Group 21. I/O Ports Port 3: P30, P31 1: ON 0: OFF ODR0, ODR1 Enable peripheral module output PODR Peripheral module output signal Input signal of peripheral module/interrupt Reading the port ISEL bit RTC time capture event input signal Note 1.
Page 436 RX23W Group 21. I/O Ports Port 3: P36/EXTAL 1: ON 0: OFF ODR0, ODR1 PODR Reading the port MOSCCR.MOSTP MOFCR.MOSEL 0: ON 1: OFF Main clock Port 3: P37/XTAL 1: ON 0: OFF ODR0, ODR1 PODR Reading the port Note 1. Control signal for N-channel open-drain output. Figure 21.5 I/O Port Configuration (5) R01UH0823EJ0100 Rev.1.00...
Page 437 RX23W Group 21. I/O Ports Port 4: P40 to P46 1: ON 0: OFF PODR Reading the port ASEL bit Analog input Port 4: P47 1: ON 0: OFF PODR Reading the port ASEL bit Analog input CLKOUT_RF Note 1. Specify from the Bluetooth middleware. Figure 21.6 I/O Port Configuration (6) R01UH0823EJ0100 Rev.1.00...
Page 438 RX23W Group 21. I/O Ports Port B: PB0, PB1, PB3, PB5, PB7 1: ON Port C: PC7 0: OFF ODR0, ODR1 Enable peripheral module output PODR Peripheral module output signal Input signal of peripheral module/interrupt Reading the port ISEL bit Note 1.
Page 439 RX23W Group 21. I/O Ports Port C: PC4 1: ON 0: OFF ODR0, ODR1 Enable peripheral module output PODR Peripheral module output signal Input signal of peripheral module/interrupt Reading the port ISEL bit CTSU channel enable control register Sensor drive pulse Port D: PD3 1: ON 0: OFF...
Page 440 RX23W Group 21. I/O Ports Port E: PE0 to PE4 1: ON 0: OFF ODR0, ODR1 Enable peripheral module output PODR Peripheral module output signal Input signal of peripheral module/ interrupt Reading the port ISEL bit ASEL bit Analog input Note 1.
Page 441: Register Descriptions
RX23W Group 21. I/O Ports 21.3 Register Descriptions 21.3.1 Port Direction Register (PDR) Address(es): PORT0.PDR 0008 C000h, PORT1.PDR 0008 C001h, PORT2.PDR 0008 C002h, PORT3.PDR 0008 C003h, PORT4.PDR 0008 C004h, PORTB.PDR 0008 C00Bh, PORTC.PDR 0008 C00Ch, PORTD.PDR 0008 C00Dh, PORTE.PDR 0008 C00Eh, PORTJ.PDR 0008 C012h Value after reset: Symbol Bit Name...
Page 442: Port Output Data Register (Podr)
RX23W Group 21. I/O Ports 21.3.2 Port Output Data Register (PODR) Address(es): PORT0.PODR 0008 C020h, PORT1.PODR 0008 C021h, PORT2.PODR 0008 C022h, PORT3.PODR 0008 C023h, PORT4.PODR 0008 C024h, PORTB.PODR 0008 C02Bh, PORTC.PODR 0008 C02Ch, PORTD.PODR 0008 C02Dh, PORTE.PODR 0008 C02Eh, PORTJ.PODR 0008 C032h Value after reset: Symbol Bit Name...
Page 443: Port Input Data Register (Pidr)
RX23W Group 21. I/O Ports 21.3.3 Port Input Data Register (PIDR) Address(es): PORT0.PIDR 0008 C040h, PORT1.PIDR 0008 C041h, PORT2.PIDR 0008 C042h, PORT3.PIDR 0008 C043h, PORT4.PIDR 0008 C044h, PORTB.PIDR 0008 C04Bh, PORTC.PIDR 0008 C04Ch, PORTD.PIDR 0008 C04Dh, PORTE.PIDR 0008 C04Eh, PORTJ.PIDR 0008 C052h Value after reset: x: Undefined Symbol...
Page 444: Port Mode Register (Pmr)
RX23W Group 21. I/O Ports 21.3.4 Port Mode Register (PMR) Address(es): PORT0.PMR 0008 C060h, PORT1.PMR 0008 C061h, PORT2.PMR 0008 C062h, PORT3.PMR 0008 C063h, PORT4.PMR 0008 C064h, PORTB.PMR 0008 C06Bh, PORTC.PMR 0008 C06Ch, PORTD.PMR 0008 C06Dh, PORTE.PMR 0008 C06Eh, PORTJ.PMR 0008 C072h Value after reset: Symbol Bit Name...
Page 445: Open Drain Control Register 0 (Odr0)
RX23W Group 21. I/O Ports 21.3.5 Open Drain Control Register 0 (ODR0) Address(es): PORT2.ODR0 0008 C084h, PORT3.ODR0 0008 C086h, PORTB.ODR0 0008 C096h, PORTC.ODR0 0008 C098h, PORTE.ODR0 0008 C09Ch, PORTJ.ODR0 0008 C0A4h Value after reset: Symbol Bit Name Description Pm0 Output Type Select 0: CMOS output 1: N-channel open-drain Reserved...
Page 446: Open Drain Control Register 1 (Odr1)
RX23W Group 21. I/O Ports 21.3.6 Open Drain Control Register 1 (ODR1) Address(es): PORT1.ODR1 0008 C083h, PORT2.ODR1 0008 C085h, PORT3.ODR1 0008 C087h, PORTB.ODR1 0008 C097h, PORTC.ODR1 0008 C099h, PORTE.ODR1 0008 C09Dh Value after reset: Symbol Bit Name Description Pm4 Output Type Select 0: CMOS output 1: N-channel open-drain Reserved...
Page 447: Pull-Up Control Register (Pcr)
RX23W Group 21. I/O Ports 21.3.7 Pull-Up Control Register (PCR) Address(es): PORT0.PCR 0008 C0C0h, PORT1.PCR 0008 C0C1h, PORT2.PCR 0008 C0C2h, PORT3.PCR 0008 C0C3h, PORT4.PCR 0008 C0C4h, PORTB.PCR 0008 C0CBh, PORTC.PCR 0008 C0CCh, PORTD.PCR 0008 C0CDh, PORTE.PCR 0008 C0CEh, PORTJ.PCR 0008 C0D2h Value after reset: Symbol Bit Name...
Page 448: Drive Capacity Control Register (Dscr)
RX23W Group 21. I/O Ports 21.3.8 Drive Capacity Control Register (DSCR) Address(es): PORT1.DSCR 0008 C0E1h, PORT2.DSCR 0008 C0E2h, PORT3.DSCR 0008 C0E3h, PORTB.DSCR 0008 C0EBh, PORTC.DSCR 0008 C0ECh, PORTD.DSCR 0008 C0EDh, PORTE.DSCR 0008 C0EEh, PORTJ.DSCR 0008 C0F2h Value after reset: Symbol Bit Name Description Pm0 Drive Capacity Control...
Page 449: Initialization Of The Port Direction Register (Pdr)
RX23W Group 21. I/O Ports 21.4 Initialization of the Port Direction Register (PDR) Initialize reserved bits in the PDR register according to Table 21.3 and Table 21.4 .  The blank columns in Table 21.3 and Table 21.4 indicate the bits corresponding to the pins listed in Table 21.1, Specifications of I/O Ports .
Page 450: Handling Of Unused Pins
RX23W Group 21. I/O Ports 21.5 Handling of Unused Pins The configuration of unused pins is listed in Table 21.5 . Table 21.5 Unused Pin Configuration Pin Name Description VBATT Connect this pin to VCC. (Always used as mode pins) RES# Connect this pin to VCC via a pull-up resistor.
Page 451: Multi-Function Pin Controller (Mpc)
RX23W Group 22. Multi-Function Pin Controller (MPC) Multi-Function Pin Controller (MPC) 22.1 Overview The multi-function pin controller (MPC) is used to allocate input and output signals for peripheral modules and input interrupt signals to pins from among multiple ports. Table 22.1 shows the allocation of pin functions to multiple pins. The symbols  and × in the table indicate whether the pins are or are not present on the given package.
Page 452 RX23W Group 22. Multi-Function Pin Controller (MPC) Table 22.1 Allocation of Pin Functions to Multiple Pins (2/6) Package Module/Function Channel Pin Functions Allocation Port 84-pin 56-pin Multi-function timer unit 2 MTU4 MTIOC4A (input/output) ×    MTIOC4B (input/output)  ...
Page 453 RX23W Group 22. Multi-Function Pin Controller (MPC) Table 22.1 Allocation of Pin Functions to Multiple Pins (3/6) Package Module/Function Channel Pin Functions Allocation Port 84-pin 56-pin 16-bit timer pulse unit TCLKA (input)     TCLKB (input)   ...
Page 454 RX23W Group 22. Multi-Function Pin Controller (MPC) Table 22.1 Allocation of Pin Functions to Multiple Pins (4/6) Package Module/Function Channel Pin Functions Allocation Port 84-pin 56-pin Serial communications SCI8 RXD8 (input)/SMISO8 (input/output)/   interface SSCL8 (input/output) TXD8 (output)/SMOSI8 (input/output)/ ...
Page 455 RX23W Group 22. Multi-Function Pin Controller (MPC) Table 22.1 Allocation of Pin Functions to Multiple Pins (5/6) Package Module/Function Channel Pin Functions Allocation Port 84-pin 56-pin SD host interface SDHI_CLK (output) ×  SDHI_CMD (input/output) ×  SDHI_D0 (input/output) × ...
Page 456 RX23W Group 22. Multi-Function Pin Controller (MPC) Table 22.1 Allocation of Pin Functions to Multiple Pins (6/6) Package Module/Function Channel Pin Functions Allocation Port 84-pin 56-pin Comparator B CMPB2 (input)*   CVREFB2 (input)*   CMPB3 (input)*   CVREFB3 (input)* ...
Page 457: Register Descriptions
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2 Register Descriptions Registers and bits for pins that are not present due to differences according to the package are reserved. Write the value after a reset when writing to such bits. 22.2.1 Write-Protect Register (PWPR) Address(es): 0008 C11Fh B0WI PFSWE...
Page 458: P0N Pin Function Control Register (P0Npfs) (N = 3, 5, 7)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.2 P0n Pin Function Control Register (P0nPFS) (n = 3, 5, 7) Address(es): P03PFS 0008 C143h, P05PFS 0008 C145h, P07PFS 0008 C147h ASEL — — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select...
Page 459: P1N Pin Function Control Registers (P1Npfs) (N = 4 To 7)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.3 P1n Pin Function Control Registers (P1nPFS) (n = 4 to 7) Address(es): P14PFS 0008 C14Ch, P15PFS 0008 C14Dh, P16PFS 0008 C14Eh, P17PFS 0008 C14Fh ASEL ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0...
Page 460: P2N Pin Function Control Register (P2Npfs) (N = 1, 2, 5 To 7)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.4 P2n Pin Function Control Register (P2nPFS) (n = 1, 2, 5 to 7) Address(es): P21PFS 0008 C151h, P22PFS 0008 C152h, P25PFS 0008 C155h, P26PFS 0008 C156h, P27PFS 0008 C157h ASEL — — PSEL[4:0] Value after reset: Symbol...
Page 461: P3N Pin Function Control Registers (P3Npfs) (N = 0, 1)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.5 P3n Pin Function Control Registers (P3nPFS) (n = 0, 1) Address(es): P30PFS 0008 C158h, P31PFS 0008 C159h — ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function.
Page 462: P4N Pin Function Control Registers (P4Npfs) (N = 0 To 7)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.6 P4n Pin Function Control Registers (P4nPFS) (n = 0 to 7) Address(es): P40PFS 0008 C160h, P41PFS 0008 C161h, P42PFS 0008 C162h, P43PFS 0008 C163h, P44PFS 0008 C164h, P45PFS 0008 C165h, P46PFS 0008 C166h, P47PFS 0008 C167h ASEL —...
Page 463: Pbn Pin Function Control Registers (Pbnpfs) (N = 0, 1, 3, 5, 7)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.7 PBn Pin Function Control Registers (PBnPFS) (n = 0, 1, 3, 5, 7) Address(es): PB0PFS 0008 C198h, PB1PFS 0008 C199h, PB3PFS 0008 C19Bh, PB5PFS 0008 C19Dh, PB7PFS 0008 C19Fh — ISEL — PSEL[4:0] Value after reset: Symbol...
Page 464: Pcn Pin Function Control Registers (Pcnpfs) (N = 0, 2 To 7)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.8 PCn Pin Function Control Registers (PCnPFS) (n = 0, 2 to 7) Address(es): PC0PFS 0008 C1A0h, PC2PFS 0008 C1A2h, PC3PFS 0008 C1A3h, PC4PFS 0008 C1A4h, PC5PFS 0008 C1A5h, PC6PFS 0008 C1A6h, PC7PFS 0008 C1A7h —...
Page 465: Pdn Pin Function Control Registers (Pdnpfs) (N = 3)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.9 PDn Pin Function Control Registers (PDnPFS) (n = 3) Address(es): PD3PFS 0008 C1ABh ASEL ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below.
Page 466: Pen Pin Function Control Registers (Penpfs) (N = 0 To 4)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.10 PEn Pin Function Control Registers (PEnPFS) (n = 0 to 4) Address(es): PE0PFS 0008 C1B0h, PE1PFS 0008 C1B1h, PE2PFS 0008 C1B2h, PE3PFS 0008 C1B3h, PE4PFS 0008 C1B4h ASEL ISEL — PSEL[4:0] Value after reset: Symbol Bit Name Description...
Page 467 RX23W Group 22. Multi-Function Pin Controller (MPC) Table 22.12 Register Settings for Input/Output Pin Function in 56-Pin PSEL[4:0] Settings 00000b Hi-Z (initial value) 00001b MTIOC4A MTIOC4B MTIOC4D 00010b — — MTIOC1A 00111b — POE8# — 01001b — CLKOUT CLKOUT 10111b —...
Page 468: Pjn Pin Function Control Registers (Pjnpfs) (N = 3)
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.2.11 PJn Pin Function Control Registers (PJnPFS) (n = 3) Address(es): PJ3PFS 0008 C1D3h — — — PSEL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below.
Page 469: Usage Notes
RX23W Group 22. Multi-Function Pin Controller (MPC) 22.3 Usage Notes 22.3.1 Procedure for Specifying Input/Output Pin Function Use the following procedure to specify the input/output pin functions. (1) Clear the port mode register (PMR) to 0 to select the general I/O port function. (2) Specify the assignments of input/output signals for peripheral functions to the desired pins.
Page 470: Note On Using Analog Functions
RX23W Group 22. Multi-Function Pin Controller (MPC) Table 22.14 Register Settings PmnPFS Item PMR.Bn PDR.Bn ASEL ISEL PSEL[4:0] Point to Note After a reset 00000b Pins function as general input port pins after release from the reset state. General input Set the ISEL bit to 1 if these are multiplexed with interrupt inputs.
Page 471: Multi-Function Timer Pulse Unit 2 (Mtu2A)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Multi-Function Timer Pulse Unit 2 (MTU2a) In this section, “PCLK” is used to refer to PCLKA. 23.1 Overview This MCU has an on-chip multi-function timer pulse unit 2 (MTU). Each unit comprises a 16-bit timer with five channels (MTU0 to MTU4).
Page 472 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.2 MTU Functions (1/2) Item MTU0 MTU1 MTU2 MTU3 MTU4 Count clocks PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/64 PCLK/64 PCLK/64 PCLK/64 PCLK/64 MTCLKA...
Page 473 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.2 MTU Functions (2/2) Item MTU0 MTU1 MTU2 MTU3 MTU4 Interrupt sources 7 sources 4 sources 4 sources 5 sources 5 sources  Compare match  Compare match  Compare match ...
Page 474 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Interrupt request signals MTU3: TGIA3 TGIB3 I/O pins TGIC3 MTU3: MTIOC3A TGID3 MTIOC3B TCIV3 MTIOC3C MTU4: TGIA4 MTIOC3D TGIB4 MTU4: MTIOC4A TGIC4 MTIOC4B TGID4 MTIOC4C TCIV4 MTIOC4D Clock input Internal peripheral bus Internal clock: PCLK/1 PCLK/4...
Page 475 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.3 lists the I/O pins to be used by the MTU. Table 23.3 MTU I/O Pins Module Symbol Pin Name Function MTCLKA Input External clock A input pin (MTU1 phase counting mode A phase input) MTCLKB Input External clock B input pin (MTU1 phase counting mode B phase input)
Page 476: Register Descriptions
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2 Register Descriptions 23.2.1 Timer Control Register (TCR) Address(es): MTU0.TCR 000D 0B00h, MTU1.TCR 000D 0B80h, MTU2.TCR 000D 0C00h, MTU3.TCR 000D 0A00h, MTU4.TCR 000D 0A01h CCLR[2:0] CKEG[1:0] TPSC[2:0] Value after reset: Symbol Bit Name Description b2 to b0...
Page 477 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.4 CCLR[2:0] (MTU0, MTU3, and MTU4) Bit 7 Bit 6 Bit 5 Channel CCLR[2] CCLR[1] CCLR[0] Description MTU0, TCNT clearing disabled MTU3, TCNT cleared by TGRA compare match/input capture MTU4 TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing in another channel performing synchronous clearing/synchronous operation*...
Page 478 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.7 TPSC[2:0] (MTU1) Bit 2 Bit 1 Bit 0 Channel TPSC[2] TPSC[1] TPSC[0] Description MTU1 Internal clock: counts on PCLK/1 Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock: counts on MTCLKA pin input External clock: counts on MTCLKB pin input...
Page 479: Timer Mode Register (Tmdr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.2 Timer Mode Register (TMDR) Address(es): MTU0.TMDR 000D 0B01h, MTU1.TMDR 000D 0B81h, MTU2.TMDR 000D 0C01h, MTU3.TMDR 000D 0A02h, MTU4.TMDR 000D 0A03h — MD[3:0] Value after reset: Symbol Bit Name Description b3 to b0 MD[3:0] Mode Select These bits specify the timer operating mode.
Page 480 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) BFA Bit (Buffer Operation A) This bit specifies normal operation for the TGRA register or buffered operation of the combination of registers TGRA and TGRC. When the TGRC register is used as a buffer register, the TGRC input capture/output compare does not take place in modes other than complementary PWM mode, but compare match with the TGRC register occurs in complementary PWM mode.
Page 481: Timer I/O Control Register (Tior)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.3 Timer I/O Control Register (TIOR)  MTU0.TIORH, MTU1.TIOR, MTU2.TIOR, MTU3.TIORH, MTU4.TIORH Address(es): MTU0.TIORH 000D 0B02h, MTU1.TIOR 000D 0B82h, MTU2.TIOR 000D 0C02h, MTU3.TIORH 000D 0A04h, MTU4.TIORH 000D 0A06h IOB[3:0] IOA[3:0] Value after reset: Symbol Bit Name Description...
Page 482 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) The MTU has a total of seven TIOR registers, one for MTU0, MTU1, and MTU2, two each for MTU3, and MTU4. The TIOR register should be set when the TMDR register is set to select normal mode, PWM mode, or phase counting mode.
Page 483 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.12 TIOR (MTU1) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU1.TGRB Function MTIOC1B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 484 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.13 TIOR (MTU2) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU2.TGRB Function MTIOC2B Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 485 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.15 TIORL (MTU3) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD[3] IOD[2] IOD[1] IOD[0] MTU3.TGRD Function MTIOC3D Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 486 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.17 TIORL (MTU4) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD[3] IOD[2] IOD[1] IOD[0] MTU4.TGRD Function MTIOC4D Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 487 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.19 TIORL (MTU0) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] MTU0.TGRC Function MTIOC0C Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 488 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.21 TIOR (MTU2) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU2.TGRA Function MTIOC2A Pin Function Output compare register Output prohibited Initial output is low. Low output at compare match.
Page 489 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.23 TIORL (MTU3) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] MTU3.TGRC Function MTIOC3C Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 490 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.25 TIORL (MTU4) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] MTU4.TGRC Function MTIOC4C Pin Function Output compare register* Output prohibited Initial output is low. Low output at compare match.
Page 491: Timer Interrupt Enable Register (Tier)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.4 Timer Interrupt Enable Register (TIER)  MTU0.TIER, MTU3.TIER Address(es): MTU0.TIER 000D 0B04h, MTU3.TIER 000D 0A08h TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Value after reset:  MTU1.TIER, MTU2.TIER Address(es): MTU1.TIER 000D 0B84h, MTU2.TIER 000D 0C04h TTGE —...
Page 492 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TGIEA and TGIEB Bits (TGR Interrupt Enable A and B) Each bit enables or disables interrupt requests (TGIm) (m = A, B). TGIEC and TGIED Bits (TGR Interrupt Enable C and D) Each bit enables or disables interrupt requests (TGIm) in MTU0, MTU3, and MTU4 (m = C, D).
Page 493: Timer Status Register (Tsr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.5 Timer Status Register (TSR) Address(es): MTU0.TSR 000D 0B05h, MTU1.TSR 000D 0B85h, MTU2.TSR 000D 0C05h, MTU3.TSR 000D 0A2Ch, MTU4.TSR 000D 0A2Dh TCFD — — — — — — — Value after reset: x: Undefined Symbol Bit Name...
Page 494: Timer Buffer Operation Transfer Mode Register (Tbtm)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.6 Timer Buffer Operation Transfer Mode Register (TBTM)  MTU0.TBTM Address(es): MTU0.TBTM 000D 0B26h — — — — — TTSE TTSB TTSA Value after reset:  MTU3.TBTM, MTU4.TBTM Address(es): MTU3.TBTM 000D 0A38h, MTU4.TBTM 000D 0A39h —...
Page 495: Timer Input Capture Control Register (Ticcr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.7 Timer Input Capture Control Register (TICCR) Address(es): MTU1.TICCR 000D 0B90h — — — — I2BE I2AE I1BE I1AE Value after reset: Symbol Bit Name Description I1AE Input Capture Enable 0: Does not include the MTIOC1A pin in the MTU2.TGRA input capture conditions 1: Includes the MTIOC1A pin in the MTU2.TGRA input capture conditions...
Page 496: Timer A/D Converter Start Request Control Register (Tadcr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.8 Timer A/D Converter Start Request Control Register (TADCR) Address(es): MTU4.TADCR 000D 0A40h BF[1:0] — — — — — — UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Value after reset: Symbol Bit Name Description...
Page 497: Timer A/D Converter Start Request Cycle Set Registers A And B (Tadcora And Tadcorb)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.26 Setting of Transfer Timing by TADCR.BF[1:0] Bits Bit 15 Bit 14 Description In Complementary PWM In Reset-Synchronized BF[1] BF[0] Mode PWM Mode In PWM Mode 1 In Normal Mode Data is not transferred Data is not transferred Data is not transferred...
Page 498: Timer A/D Converter Start Request Cycle Set Buffer Registers A And B (Tadcobra And Tadcobrb)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.10 Timer A/D Converter Start Request Cycle Set Buffer Registers A and B (TADCOBRA and TADCOBRB) Address(es): MTU4.TADCOBRA 000D 0A48h, MTU4.TADCOBRB 000D 0A4Ah Value after reset: Note: MTU4.TADCOBRA and MTU4.TADCOBRB must not be accessed in 8-bit units; they should be accessed in 16- bit units.
Page 499: Timer General Register (Tgr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.12 Timer General Register (TGR) Address(es): MTU0.TGRA 000D 0B08h, MTU0.TGRB 000D 0B0Ah, MTU0.TGRC 000D 0B0Ch, MTU0.TGRD 000D 0B0Eh, MTU0.TGRE 000D 0B20h, MTU0.TGRF 000D 0B22h, MTU1.TGRA 000D 0B88h, MTU1.TGRB 000D 0B8Ah, MTU2.TGRA 000D 0C08h, MTU2.TGRB 000D 0C0Ah, MTU3.TGRA 000D 0A18h, MTU3.TGRB 000D 0A1Ah, MTU3.TGRC 000D 0A24h, MTU3.TGRD 000D 0A26h, MTU4.TGRA 000D 0A1Ch, MTU4.TGRB 000D 0A1Eh, MTU4.TGRC 000D 0A28h, MTU4.TGRD 000D 0A2Ah Value after reset:...
Page 500: Timer Start Registers (Tstr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.13 Timer Start Registers (TSTR) Address(es): MTU.TSTR 000D 0A80h CST4 CST3 — — — CST2 CST1 CST0 Value after reset: Symbol Bit Name Description CST0 Counter Start 0 0: MTU0.TCNT performs count stop 1: MTU0.TCNT performs count operation CST1 Counter Start 1...
Page 501: Timer Synchronous Registers (Tsyr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.14 Timer Synchronous Registers (TSYR) Address(es): MTU.TSYR 000D 0A81h SYNC4 SYNC3 — — — SYNC2 SYNC1 SYNC0 Value after reset: Symbol Bit Name Description SYNC0 Timer Synchronous Operation 0 0: MTU0.TCNT operates independently (TCNT setting/clearing is not related to other channels) 1: MTU0.TCNT performs synchronous operation.
Page 502: Timer Read/Write Enable Registers (Trwer)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.15 Timer Read/Write Enable Registers (TRWER) Address(es): MTU.TRWER 000D 0A84h — — — — — — — Value after reset: Symbol Bit Name Description Read/Write Enable 0: Read/write access to the registers is disabled 1: Read/write access to the registers is enabled b7 to b1 —...
Page 503: Timer Output Master Enable Registers (Toer)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.16 Timer Output Master Enable Registers (TOER) Address(es): MTU.TOER 000D 0A0Ah — — OE4D OE4C OE3D OE4B OE4A OE3B Value after reset: Symbol Bit Name Description OE3B Master Enable MTIOC3B 0: MTU output is disabled* 1: MTU output is enabled OE4A Master Enable MTIOC4A...
Page 504: Timer Output Control Registers 1 (Tocr1)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.17 Timer Output Control Registers 1 (TOCR1) Address(es): MTU.TOCR1 000D 0A0Eh — PSYE — — TOCL TOCS OLSN OLSP Value after reset: Symbol Bit Name Description OLSP Output Level Select P Refer to Table 23.27.
Page 505 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.27 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up-Counting Down-Counting High High High High Table 23.28 Output Level Select Function Bit 1 Function Compare Match Output OLSN...
Page 506: Timer Output Control Registers 2 (Tocr2)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.18 Timer Output Control Registers 2 (TOCR2) Address(es): MTU.TOCR2 000D 0A0Fh BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Value after reset: Symbol Bit Name Description OLS1P Output Level Select 1P* This bit selects the output level on MTIOC3B in reset-synchronized PWM mode and complementary PWM mode.
Page 507 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.31 MTIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up-Counting Down-Counting High High High High Table 23.32 MTIOC4C Output Level Select Function Bit 3 Function Compare Match Output...
Page 508: Timer Output Level Buffer Registers (Tolbr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.19 Timer Output Level Buffer Registers (TOLBR) Address(es): MTU.TOLBR 000D 0A36h — — OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Value after reset: Symbol Bit Name Description OLS1P Output Level Select 1P Specify the buffer value to be transferred to the OLS1P bit in TOCR2.
Page 509: Timer Gate Control Registers (Tgcr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.20 Timer Gate Control Registers (TGCR) Address(es): MTU.TGCR 000D 0A0Dh — Value after reset: Symbol Bit Name Description Output Phase Switch These bits turn on or off the positive-phase/negative-phase output. The setting of these bits is valid only when the TGCR.FB bit is set to 1. In this case, the setting of b0 to b2 is used instead of the external input.
Page 510: Timer Subcounters (Tcnts)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.36 Output Level Select Function Bit 2 Bit 1 Bit 0 Function MTIOC3B MTIOC4A MTIOC4B MTIOC3D MTIOC4C MTIOC4D U Phase V Phase W Phase U Phase V Phase W Phase 23.2.21 Timer Subcounters (TCNTS) Address(es): MTU.TCNTS 000D 0A20h...
Page 511: Timer Cycle Data Registers (Tcdr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.23 Timer Cycle Data Registers (TCDR) Address(es): MTU.TCDR 000D 0A14h Value after reset: Note: The TCDR registers must not be accessed in 8-bit units; they should be accessed in 16-bit units. The TCDR registers specify the count value to switch the count direction of the TCNTS counter.
Page 512: Timer Interrupt Skipping Set Registers (Titcr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.25 Timer Interrupt Skipping Set Registers (TITCR) Address(es): MTU.TITCR 000D 0A30h T3AEN T3ACOR[2:0] T4VEN T4VCOR[2:0] Value after reset: Symbol Bit Name Description b2 to b0 T4VCOR[2:0] TCIV4 Interrupt Skipping Count These bits specify the TCIV4 interrupt skipping count within Setting the range from 0 to 7.* For details, refer to Table 23.37.
Page 513: Timer Interrupt Skipping Counters (Titcnt)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.26 Timer Interrupt Skipping Counters (TITCNT) Address(es): MTU.TITCNT 000D 0A31h — T3ACNT[2:0] — T4VCNT[2:0] Value after reset: Symbol Bit Name Description b2 to b0 T4VCNT[2:0] TCIV4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV4 interrupt source occurs.
Page 514: Timer Buffer Transfer Set Registers (Tbter)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.27 Timer Buffer Transfer Set Registers (TBTER) Address(es): MTU.TBTER 000D 0A32h — — — — — — BTE[1:0] Value after reset: Symbol Bit Name Description b1, b0 BTE[1:0] Buffer Transfer Disable and These bits enable or disable transfer from the buffer registers used Interrupt Skipping Link Setting in complementary PWM mode to the temporary registers and...
Page 515: Timer Dead Time Enable Registers (Tder)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.28 Timer Dead Time Enable Registers (TDER) Address(es): MTU.TDER 000D 0A34h — — — — — — — TDER Value after reset: Symbol Bit Name Description TDER Dead Time Enable 0: No dead time is generated R/(W) 1: Dead time is generated* b7 to b1...
Page 516: Timer Waveform Control Registers (Twcr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.29 Timer Waveform Control Registers (TWCR) Address(es): MTU.TWCR 000D 0A60h — — — — — — Value after reset: Symbol Bit Name Description Initial Output Inhibition 0: Initial value specified in TOCR is output R/(W) Enable 1: Initial output is inhibited...
Page 517: Noise Filter Control Registers (Nfcr)
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.2.30 Noise Filter Control Registers (NFCR) Address(es): MTU0.NFCR 000D 0A90h, MTU1.NFCR 000D 0A91h, MTU2.NFCR 000D 0A92h, MTU3.NFCR 000D 0A93h, MTU4.NFCR 000D 0A94h — — NFCS[1:0] NFDEN NFCEN NFBEN NFAEN Value after reset: Symbol Bit Name Description...
Page 518: Bus Master Interface
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) NFCS[1:0] Bits (Noise Filter Clock Select) These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the selected sampling interval before setting the input-capture function. When the NFCS[1:0] bits are set to 11b, selecting the external clock as the source to drive counting, wait for two cycles of the external clock before setting the input- capture function.
Page 519: Operation
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3 Operation 23.3.1 Basic Functions Each channel has the TCNT counter and the TGR register. The TCNT counter performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR register can be used as an input capture register or an output compare register.
Page 520 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the MTU’s TCNT counters are all designated as free-running counters. When the relevant CSTn bit in the TSTR register is set to 1, the corresponding TCNT counter starts up-count operation as a free-running counter.
Page 521 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Waveform Output by Compare Match The MTU can output low or high or toggle output from the corresponding output pin using compare match. (a) Example of Procedure for Setting Waveform Output by Compare Match Figure 23.7 shows an example of the procedure for setting waveform output by compare match.
Page 522 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Examples of Waveform Output Operation Figure 23.8 shows an example of low output and high output. In this example, the TCNT counter has been designated as a free-running counter, and settings have been made so that high is output by compare match A and low is output by compare match B.
Page 523 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Input Capture Function The TCNT value can be transferred to the TGR register on detection of the input edge of the MTIOCnm (n = 0 to 4; m = A to D) pin. The rising edge, falling edge, or both edges can be selected as the detection edge.
Page 524 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Example of Input Capture Operation Figure 23.11 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the MTIOCnA pin input capture input edge, the falling edge has been selected as the MTIOCnB pin input capture input edge, and counter clearing by the TGRB input capture has been designated for the TCNT counter.
Page 525: Synchronous Operation
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be modified simultaneously (synchronous setting). In addition, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in the TCR register.
Page 526 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Example of Synchronous Operation Figure 23.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for MTU0 to MTU2, compare match of the MTU0.TGRB register has been set as the counter clearing source in MTU0, and synchronous clearing has been set for the counter clearing source in MTU1 and MTU2.
Page 527: Buffer Operation
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.3 Buffer Operation Buffer operation, provided for MTU0, MTU3, and MTU4, enables registers TGRC and TGRD to be used as buffer registers. In MTU0, TGRF register can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 528 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of Buffer Operation Setting Procedure Figure 23.16 shows an example of the buffer operation setting procedure. [1] Designate the TGR register as an input capture Buffer operation register or output compare register by means of the TIOR register.
Page 529 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) When TGR register is an Input Capture Register Figure 23.18 shows an operation example in which the TGRA register has been designated as an input capture register, and buffer operation has been designated for registers TGRA and TGRC. Counter clearing by TGRA input capture has been set for the TCNT counter, and both rising and falling edges have been selected as the MTIOCnA pin input capture input edge.
Page 530 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for MTU0 or in PWM mode 1 for MTU3 and MTU4 by setting the timer buffer operation transfer mode registers (MTU0.TBTM, MTU3.TBTM, and MTU4.TBTM).
Page 531: Cascaded Operation
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.4 Cascaded Operation In cascaded operation, 16-bit counters in different two channels are used together as a 32-bit counter. This function works when overflow/underflow of the MTU2.TCNT counter is selected as the count clock for MTU1 through the TCR.TPSC[2:0] bits.
Page 532 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of Cascaded Operation Setting Procedure Figure 23.20 shows an example of the cascaded operation setting procedure. [1] Set the MTU1.TCR.TPSC[2:0] bits to 111b to Cascaded operation select MTU2.TCNT overflow/underflow counting. Set cascading [2] Set the TSTR.CSTn bit for the upper and lower channels to 1 to start the count operation.
Page 533 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Cascaded Operation Example (b) Figure 23.22 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected the MTIOC1A rising edge for the input capture timing while the MTU2.TIOR.IOA[3:0] bits have selected the MTIOC2A rising edge for the input capture timing.
Page 534 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (4) Cascaded Operation Example (c) Figure 23.23 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE and I1AE bits in TICCR register have been set to 1 to include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA input capture conditions, respectively.
Page 535 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (5) Cascaded Operation Example (d) Figure 23.24 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected occurrence of MTU0.TGRA compare match or input capture for the input capture timing while the MTU2.TIOR.IOA[3:0] bits have selected the MTIOC2A rising edge for the input capture timing.
Page 536: Pwm Modes
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.5 PWM Modes PWM modes are provided to output PWM waveforms from the external pins. The output level can be selected as low, high, or toggle output in response to a compare match of each TGR register. PWM waveforms in the range of 0% to 100% duty cycle can be output according to the TGR settings.
Page 537 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of PWM Mode Setting Procedure Figure 23.25 shows an example of the PWM mode setting procedure. [1] Enable TOER output when outputting a waveform from the PWM mode MTIOC pin of MTU3 and MTU4. [2] Set the TCR.TPSC[2:0] bits to select the count clock source.
Page 538 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Figure 23.27 shows an example of operation in PWM mode 2. In this example, synchronous operation is designated for MTU0 and MTU1, MTU1.TGRB compare match is set as the TCNT clearing source, and a low level is set as the initial output value and a high level as the output value for the other TGR registers (MTU0.TGRA to MTU0.TGRC and MTU1.TGRA), outputting 4-phase PWM waveforms.
Page 539 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Figure 23.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode 1. In this example, TGRA compare match is set as the TCNT clearing source, a low level is set as the initial output value and output value for the TGRA register, and a high level is set as the output value for the TGRB register.
Page 540: Phase Counting Mode
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.6 Phase Counting Mode When phase counting mode is specified, an external clock is selected as the count clock and the TCNT counter operates as an up-counter/down-counter regardless of the setting of the TCR.TPSC[2:0] bits and TCR.CKEG[1:0] bits. However, the functions of the TCR.CCLR[2:0] bits and of registers TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used.
Page 541 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Examples of Phase Counting Mode Operation In phase counting mode, the TCNT counter is incremented or decremented according to the phase difference between two external clocks. There are four modes according to the count conditions. (a) Phase Counting Mode 1 Figure 23.30 shows an example of operation in phase counting mode 1, and Table 23.45 lists the TCNT up-counting and down-counting conditions.
Page 542 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Phase Counting Mode 2 Figure 23.31 shows an example of operation in phase counting mode 2, and Table 23.46 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value...
Page 543 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Phase Counting Mode 3 Figure 23.32 shows an example of operation in phase counting mode 3, and Table 23.47 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Down-counting...
Page 544 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (d) Phase Counting Mode 4 Figure 23.33 shows an example of operation in phase counting mode 4, and Table 23.48 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value...
Page 545 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Phase Counting Mode Application Example Figure 23.34 shows an example in which MTU1 is in phase counting mode, and MTU1 is coupled with MTU0 to input 2-phase encoder pulses of a servo motor in order to detect position or speed. MTU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to MTCLKA and MTCLKB.
Page 546: Reset-Synchronized Pwm Mode
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, six phases of positive and negative PWM waveforms that share a common wave transition point can be output by combining MTU3 and MTU4. When set for reset-synchronized PWM mode, the MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, and MTIOC4D pins function as PWM output pins and the MTU3.TCNT counter functions as an up-counter.
Page 547 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of Procedure for Setting Reset-Synchronized PWM Mode Figure 23.35 shows an example of procedure for setting the reset-synchronized PWM mode. Set the CST3 and CST4 bits in the TSTR register to 0 to stop the Reset-synchronized PWM mode TCNT operation.
Page 548 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Example of Reset-Synchronized PWM Mode Operation Figure 23.36 shows an example of operation in the reset-synchronized PWM mode. Counters MTU3.TCNT and MTU4.TCNT operate as up-counters. The counters are cleared when a compare match occurs between the MTU3.TCNT counter and the MTU3.TGRA register, and then begin incrementing from 0000h.
Page 549: Complementary Pwm Mode
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.8 Complementary PWM Mode In complementary PWM mode, dead time can be set for PWM waveforms to be output. The dead time is the period during which the upper and lower arm transistors are set to the inactive level in order to prevent short-circuiting of the arms.
Page 550 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TCBR MTU3.TGRC TDDR TCDR MTU3.TGRA PWM cycle Comparator Match output signal PWM output 1 PWM output 2 TCNTS MTU3.TCNT MTU4.TCNT PWM output 3 PWM output 4 PWM output 5 Comparator PWM output 6 Match External cutoff signal...
Page 551 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Example of Complementary PWM Mode Setting Procedure Figure 23.38 shows an example of the complementary PWM mode setting procedure. Set bits CST3 and CST4 in the TSTR register to 0 to stop TCNT operation. Complementary PWM mode Specify complementary PWM mode while counters MTU3.TCNT and MTU4.TCNT are stopped.
Page 552 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Outline of Complementary PWM Mode Operation In complementary PWM mode, six phases (three positive and three negative) of PWM waveforms can be output. Figure 23.39 illustrates counter operation in complementary PWM mode, and Figure 23.40 shows an example of operation in complementary PWM mode.
Page 553 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Register Operation In complementary PWM mode, nine registers (compare registers, buffer registers, and temporary registers) are used to control the duty ratio for the PWM output. Figure 23.40 shows an example of operation in complementary PWM mode. Registers MTU3.TGRB, MTU4.TGRA, and MTU4.TGRB are constantly compared with the counters to generate PWM waveforms.
Page 554 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Transfer from temporary register Transfer from temporary register to compare register to compare register MTU3.TGRA TCNTS TCDR MTU3.TCNT MTU4.TGRA MTU4.TCNT MTU4.TGRC TDDR 0000h Buffer register 6400h 0080h MTU4.TGRC 0080h Temporary register 6400h Compare register 6400h...
Page 555 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Initial Setting In complementary PWM mode, there are six registers that require initial setting. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with the TMDR.MD[3:0] bits, initial values should be set in the following registers.
Page 556 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Transfer from temporary register to compare register MTU3.TGRA = TCDR + 1 TCNTS TCDR MTU3.TCNT MTU4.TCNT MTU4.TGRA MTU4.TGRC TDDR = 1 0000h Buffer register Data 1 Data 2 MTU4.TGRC Data 1 Data 2 Temporary register Compare register...
Page 557 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (g) PWM Cycle Setting In complementary PWM mode, the PWM cycle is set in two registers — the MTU3.TGRA register, in which the MTU3.TCNT counter upper limit value is set, and the TCDR register, in which the MTU4.TCNT counter upper limit value is set.
Page 558 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU4.TGRD register after writing data to the registers to be updated. In this case, the data written to the MTU4.TGRD register should be the same as the data prior to the write operation. Figure 23.43 Example of Data Updating in Complementary PWM Mode R01UH0823EJ0100 Rev.1.00...
Page 559 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the TOCR1 register or bits OLS1N to OLS3N and OLS1P to OLS3P in the TOCR2 register. This initial output is the non-active level of the PWM output and continues from when complementary PWM mode is set with the TMDR register until the MTU4.TCNT counter exceeds the value set in the TDDR register.
Page 560 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer output control register settings TOCR1.OLSN bit = 0 (initial output: high; active level: low) TOCR1.OLSP bit = 0 (initial output: high; active level: low) MTU3.TCNT values MTU3.TCNT MTU4.TCNT TDDR MTU4.TGRA Time Initial output Positive-phase...
Page 561 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Method for Generating PWM Output in Complementary PWM Mode In complementary PWM mode, six phases (three positive and three negative) of PWM waveforms can be output. Dead time can be set for PWM waveforms to be output. A PWM waveform is generated by output of the level selected in the timer output control register in the event of a compare match between a counter and a compare register.
Page 562 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) T1 interval T2 interval T1 interval Counter for generating MTU3.TGRA a turn-off timing Counter for generating TEMP2 a turn-on timing TCDRA MTU4.TGRA TDDRA 0000h Positive-phase Don't care output Negative-phase output Output waveform is active-low. Buffer operation is set for transfer at the crest and trough.
Page 563 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 0% and 100% Duty Cycle Output in Complementary PWM Mode In complementary PWM mode, 0% and 100% duty cycle PWM waveforms can be output as required. Figure 23.49 to Figure 23.53 show output examples. A 100% duty cycle waveform is output when the data register value is set to 0000h.
Page 564 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) T1 interval T2 interval T1 interval Counter for generating MTU3.TGRA TEMP2 a turn-off timing Counter for generating a turn-on timing TCDRA MTU4.TGRA TDDRA 0000h 0% duty cycle output Positive-phase Don't care output 100% duty cycle output Negative-phase...
Page 565 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) T1 interval T2 interval T1 interval Counter for generating a turn-off timing MTU3.TGRA Counter for generating MTU4.TGRA a turn-on timing TCDRA MTU3.TCNT MTU4.TCNT TDDRA 0000h Don't care 0% duty cycle output Positive-phase output 100% duty cycle output...
Page 566 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (m) Counter Clearing by Another Channel In complementary PWM mode, counters MTU3.TCNT, MTU4.TCNT, and TCNTS can be cleared by another channel source when a mode for synchronization with another channel is specified by the TSYR register and synchronous clearing is selected with the MTU3.TCR.CCLR[2:0] bits.
Page 567 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the TWCR.WRE bit to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval (Tb2 interval) at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing.
Page 568 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in Figure 23.57 .
Page 569 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous clearing WRE bit = 1 MTU3.TGRA TCDR MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDR 0000h Positive-phase output Negative-phase output Output waveform is active-low. Figure 23.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 23.56;...
Page 570 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous clearing WRE bit = 1 MTU3.TGRA TCDR MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDR 0000h Positive-phase output Negative-phase output Output waveform is active-low. Figure 23.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 23.56;...
Page 571 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (o) Counter Clearing by MTU3.TGRA Compare Match In complementary PWM mode, counters MTU3.TCNT, MTU4.TCNT, and TCNTS can be cleared by MTU3.TGRA compare match when the TWCR.CCE bit is set. Figure 23.62 shows an operation example. Note: Use this function only in complementary PWM mode 1 (transfer at crest).
Page 572 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (p) Example of Waveform Output for Driving AC Synchronous Motor (Brushless DC Motor) In complementary PWM mode, a brushless DC motor can easily be controlled using the TGCR register. Figure 23.63 to Figure 23.66 show examples of brushless DC motor driving waveforms created using the TGCR register.
Page 573 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) External input MTIOC0A pin MTIOC0B pin MTIOC0C pin 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin When TGCR.BDC = 1, TGCR.N = 1, TGCR.P = 1, and TGCR.FB = 0, the high level is the active level for output.
Page 574 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) UF bit TGCR VF bit WF bit 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin When TGCR.BDC = 1, TGCR.N = 1, TGCR.P = 1, and TGCR.FB = 1, the high level is the active level for output.
Page 575 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Interrupt Skipping in Complementary PWM Mode Interrupts TGIA3 (at the crest) and TCIV4 (at the trough) in MTU3 and MTU4 can be skipped up to seven times by setting the TITCR register. Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the TBTER register.
Page 576 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (b) Example of Interrupt Skipping Operation Figure 23.69 shows an example of MTU3.TGIA interrupt skipping in which the interrupt skipping count is set to three by the TITCR.T3ACOR[2:0] bits and the TITCR.T3AEN bit is set to 1. Interrupt skipping period Interrupt skipping period MTU3.TGRA compare match...
Page 577 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the TBTER.BTE[1:0] bits. Figure 23.70 shows an example of operation when buffer transfer is disabled (BTE[1:0] = 01b).
Page 578 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.TCNT MTU4.TCNT (1) When the buffer register is modified within one carrier cycle after a TGIA3 interrupt TCNTSA TGIA3 generated TGIA3 generated MTU3. TCNT MTU4. TCNT Timing for modifying Timing for modifying the buffer register the buffer register Buffer transfer-enabled period...
Page 579 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.TCNT MTU4.TCNT TCNTSA Skipping counter TITCNT1A.T3ACNT[2:0] bits Skipping counter TITCNT1A.T4VCNT[2:0] bits Buffer transfer-enabled period (TITCNT1A.T3AEN bit is set to 1) Buffer transfer-enabled period (TITCNT1A.T4VEN bit is set to 1) Buffer transfer-enabled period (TITCNT1A.T3AEN and T4VEN bits are set to 1) Note: The skipping count is set to three.
Page 580: A/D Converter Start Request Delaying Function
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in MTU4 by making settings in registers TADCR, TADCORA, TADCORB, TADCOBRA, and TADCOBRB. The A/D converter start request delaying function compares the MTU4.TCNT counter with the MTU4.TADCORA or MTU4.TADCORB register, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN).
Page 581 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Basic Example of A/D Converter Start Request Delaying Function Operation Figure 23.74 shows a basic example of A/D converter start request signal (TRG4AN) operation when the trough of the MTU4.TCNT counter is specified for the buffer transfer timing and an A/D converter start request signal is output during MTU4.TCNT down-counting.
Page 582 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (5) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping In complementary PWM mode, A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making settings in the TADCR.ITA3AE bit, TADCR.ITA4VE bit, TADCR.ITB3AE bit, and TADCR.ITB4VE bit.
Page 583 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU4.TCNT MTU4.TADCORA TGIA3 interrupt skipping counter TCIV4 interrupt skipping counter TGIA3 A/D request-enabled period TCIV4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA3 and TCIV4 interrupt skipping When linked with TGIA3 interrupt skipping When linked with TCIV4...
Page 584: Noise Filter
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.3.10 Noise Filter Each pin for use in input capture and external pulse input to the MTU is equipped with a noise filter. The noise filter samples input signals at the sampling clock and removes the pulses of which length is less than three sampling cycles. The noise filter functionality includes enabling and disabling of the noise filter for each pin and setting of the sampling clock for each channel.
Page 585: Interrupt Sources
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.4 Interrupt Sources 23.4.1 Interrupt Sources and Priorities There are three interrupt sources; the TGR input capture/compare match, the TCNT counter overflow, and the TCNT counter underflow. Each interrupt source has its own enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
Page 586: Dtc/Dmac Activation
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TIER.TGIE bit is set to 1 when a TGR input capture/compare match occurs on a channel. The MTU has 18 input capture/compare match interrupts (six for MTU0, four each for MTU3 and MTU4, and two each for MTU1 and MTU2).
Page 587 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) A/D Converter Activation by Compare Match between MTU0.TCNT and MTU0.TGRE A compare match between the MTU0.TCNT counter and the MTU0.TGRE register activates the A/D converter. A/D converter start request signal TRG0EN is issued when a compare match occurs between the MTU0.TCNT counter and the MTU0.TGRE register.
Page 588: Operation Timing
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.5 Operation Timing 23.5.1 Input/Output Timing (1) TCNT Count Timing Figure 23.78 show the TCNT count timing for TGI interrupt in internal clock operation, Figure 23.79 shows the TCNT count timing in external clock operation (normal mode), and Figure 23.80 shows the TCNT count timing in external clock operation (phase counting mode).
Page 589 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Output Compare Output Timing A compare match signal is generated in the final state in which the TCNT counter and the TGR register match (the point at which the count value matched is updated by the TCNT counter). When a compare match signal is generated, the value set in the TIOR register is output to the output compare output pin (MTIOC pin).
Page 590 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Input Capture Signal Timing Figure 23.83 shows the input capture signal timing. PCLK Input capture input Input capture signal N + 1 N + 2 TCNT N + 2 Figure 23.83 Input Capture Input Signal Timing R01UH0823EJ0100 Rev.1.00 Page 590 of 1823...
Page 591 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 23.84 show the timing when counter clearing on compare match is specified, and Figure 23.85 shows the timing when counter clearing on input capture is specified. PCLK Compare match signal Counter clear signal...
Page 592 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (5) Buffer Operation Timing Figure 23.86 to Figure 23.88 show the timing in buffer operation. PCLK TCNT n + 1 Compare match signal TGRA, TGRB TGRC, TGRD Figure 23.86 Buffer Operation Timing (Compare Match) PCLK Input capture signal TCNT...
Page 593 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (6) Buffer Transfer Timing (Complementary PWM Mode) Figure 23.89 to Figure 23.91 show the buffer transfer timing in complementary PWM mode. PCLK TCNTS 0000h MTU4.TGRD write signal Temporary register transfer signal Buffer register Temporary register Figure 23.89...
Page 594: Interrupt Signal Timing
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.5.2 Interrupt Signal Timing (1) Timing for TGI Interrupt by Compare Match Figure 23.92 show the TGI interrupt request signal timing on compare match. PCLK TCNT count clock N + 1 TCNT Compare match signal Interrupt signal...
Page 595 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) TCIV and TCIU Interrupt Timing Figure 23.94 shows the TCIV interrupt request signal timing on overflow. Figure 23.95 shows the TCIU interrupt request signal timing on underflow. PCLK TCNT count clock TCNT (overflow) FFFFh 0000h...
Page 596: Usage Notes
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6 Usage Notes 23.6.1 Module Clock Stop Mode Setting MTU operation can be disabled or enabled using the module stop control register. MTU operation is stopped with the initial setting. Register access is enabled by releasing the module clock stop mode. For details, refer to section 11, Low Power Consumption .
Page 597: Contention Between Tcnt Write And Clear Operations
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in a TCNT write cycle, the TCNT counter clearing takes precedence and the TCNT counter write operation is not performed. Figure 23.97 shows the timing in this case.
Page 598: Contention Between Tgr Write Operation And Compare Match
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.6 Contention between TGR Write Operation and Compare Match If a compare match occurs in a TGR write cycle, the TGR register write operation is executed and the compare match signal is also generated. Figure 23.99 shows the timing in this case.
Page 599: Contention Between Buffer Register Write And Tcnt Clear Operations
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.8 Contention between Buffer Register Write and TCNT Clear Operations When the buffer transfer timing is set at the TCNT clear timing by the timer buffer operation transfer mode register (TBTM), if TCNT clearing occurs in a TGR write cycle, the data before write operation is transferred to TGR by the buffer operation.
Page 600: Contention Between Tgr Write Operation And Input Capture
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.10 Contention between TGR Write Operation and Input Capture If an input capture signal is generated in a TGR write cycle, the input capture operation takes precedence and the TGR register write operation is not performed. Figure 23.103 show the timing in this case.
Page 601: Contention Between Mtu2.Tcnt Write Operation And Overflow/Underflow In Cascaded Operation
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.12 Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation With timer counters MTU1.TCNT and MTU2.TCNT in a cascade, when a contention occurs between MTU1.TCNT counting (an MTU2.TCNT counter overflow/underflow) and the MTU2.TCNT write cycle, the MTU2.TCNT write operation is performed and the MTU1.TCNT count signal is disabled.
Page 602: Counter Value When Count Operation Is Stopped In Complementary Pwm Mode
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.13 Counter Value When Count Operation is Stopped in Complementary PWM Mode When counting operation in counters MTU3.TCNT and MTU4.TCNT is stopped in complementary PWM mode, the MTU3.TCNT counter is set to the TDDR register value and the MTU4.TCNT counter becomes 0000h. When operation is restarted in complementary PWM mode, counting begins automatically from the initial setting state.
Page 603: Buffer Operation And Compare Match Flags In Reset-Synchronized Pwm Mode
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.15 Buffer Operation and Compare Match Flags in Reset-Synchronized PWM Mode When setting buffer operation in reset-synchronized PWM mode, set the MTU4.TMDR.BFA bit and MTU4.TMDR.BFB bit to 0. Setting the MTU4.TMDR.BFA bit to 1 disables MTIOC4C pin waveform output. Setting the MTU4.TMDR.BFB bit to 1 also disables MTIOC4D pin waveform output.
Page 604: Overflow Flags In Reset-Synchronized Pwm Mode
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.16 Overflow Flags in Reset-Synchronized PWM Mode After reset-synchronized PWM mode is selected, counters MTU3.TCNT and MTU4.TCNT start counting when the TSTR.CST3 bit is set to 1. In this state, the MTU4.TCNT count clock source and count edge are determined by the MTU3.TCR register setting.
Page 605: Contention Between Overflow/Underflow And Counter Clearing
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.17 Contention between Overflow/Underflow and Counter Clearing If an overflow/underflow and counter clearing occur simultaneously, the TCNT counter clearing takes precedence and the corresponding TCIV interrupt is not generated. If an overflow and counter clearing due to an input capture occur simultaneously, an input capture interrupt signal is output and an overflow interrupt signal is not output.
Page 606: Notes On Transition From Normal Mode Or Pwm Mode 1 To Reset-Synchronized Pwm Mode
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.19 Notes on Transition from Normal Mode or PWM Mode 1 to Reset-Synchronized PWM Mode When making a transition from normal mode or PWM mode 1 to reset-synchronized PWM mode in MTU3 and MTU4, if the counter is stopped while the output pins (MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, and MTIOC4D) are held at a high level and then operation is started after a transition to reset-synchronized PWM mode, the initial pin output will not be correct.
Page 607: Notes When Complementary Pwm Mode Output Protection Functions Are Not Used
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.23 Notes When Complementary PWM Mode Output Protection Functions are Not Used The complementary PWM mode output protection functions are initially enabled. Refer to section 24, Port Output Enable 2 (POE2a) , for details. 23.6.24 Points for Caution to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode...
Page 608 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous clearing MTU3.TGRA MTU3. TCNT Tb interval Tb interval MTU4. TCNT TDDR Positive-phase output Negative-phase output Although there is no period for output of the active level over this Dead time is interval, synchronous clearing leads to output of the active level.
Page 609: Continuous Output Of Interrupt Signal In Response To A Compare Match
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.6.25 Continuous Output of Interrupt Signal in Response to a Compare Match When the TGR register is set to 0000h, PCLK/1 is set as the count clock, and compare match is set as the trigger for clearing of the count clock, the value of the TCNT counter remains 0000h, and the interrupt signal will be output continuously (i.e.
Page 610 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Write 0 to MTU4.TADCOBRA MTU4.TCNT MTU4.TADCORA MTU4.TADCOBRA A/D converter start request (TRG4AN) Complementary PWM mode An A/D converter start request is not issued during up-counting UT4AE = 1 immediately after buffer transfer (trough). DT4AE = 0 BF[1:0] = 10b (transfer at trough) UT4AE, DT4AE, BF[1:0]: Bits in TADCR...
Page 611: Mtu Output Pin Initialization
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.7 MTU Output Pin Initialization 23.7.1 Operating Modes The MTU has the following six operating modes. Waveforms can be output in any of these modes.  Normal mode (MTU0 to MTU4) ...
Page 612: Overview Of Pin Initialization Procedures And Mode Transitions In Case Of Error During Operation
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.7.3 Overview of Pin Initialization Procedures and Mode Transitions in Case of Error during Operation  When making a transition to a mode (Normal, PWM1, PWM2, or PCM) in which the pin output level is selected by the TIOR register setting, initialize the pins by means of the TIOR register setting.
Page 613 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (1) Operation When Error Occurs in Normal Mode and Operation is Restarted in Normal Mode Figure 23.116 shows a case in which an error occurs in normal mode and operation is restarted in normal mode after re- setting.
Page 614 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (2) Operation When Error Occurs in Normal Mode and Operation is Restarted in PWM Mode 1 Figure 23.117 shows a case in which an error occurs in normal mode and operation is restarted in PWM mode 1 after re- setting.
Page 615 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (4) Operation When Error Occurs in Normal Mode and Operation is Restarted in Phase Counting Mode Figure 23.119 shows a case in which an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
Page 616 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (5) Operation When Error Occurs in Normal Mode and Operation is Restarted in Complementary PWM Mode Figure 23.120 shows a case in which an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
Page 617 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (6) Operation When Error Occurs in Normal Mode and Operation is Restarted in Reset- Synchronized PWM Mode Figure 23.121 shows a case in which an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 618 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (7) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Normal Mode Figure 23.122 shows a case in which an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
Page 619 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (8) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in PWM mode 1 Figure 23.123 shows a case in which an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
Page 620 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (10) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Phase Counting Mode Figure 23.125 shows a case in which an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
Page 621 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (11) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Complementary PWM Mode Figure 23.126 shows a case in which an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
Page 622 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (12) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Reset- Synchronized PWM Mode Figure 23.127 shows a case in which an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 623 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (13) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Normal Mode Figure 23.128 shows a case in which an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
Page 624 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (14) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 1 Figure 23.129 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
Page 625 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (16) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Phase Counting Mode Figure 23.131 shows a case in which an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting.
Page 626 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (17) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in Normal Mode Figure 23.132 shows a case in which an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
Page 627 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (18) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 1 Figure 23.133 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
Page 628 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (19) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 2 Figure 23.134 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
Page 629 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (21) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Normal Mode Figure 23.136 shows a case in which an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
Page 630 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (22) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in PWM Mode 1 Figure 23.137 shows a case in which an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 631 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (23) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 23.138 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time of stopping the counter).
Page 632 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (24) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode with New Settings Figure 23.139 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (operation is restarted using new cycle and duty settings).
Page 633 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (25) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 23.140 shows a case in which an error occurs in complementary PWM mode and operation is restarted in reset- synchronized PWM mode after re-setting.
Page 634 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (26) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Normal Mode Figure 23.141 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting.
Page 635 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (27) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in PWM Mode 1 Figure 23.142 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 636 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (28) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 23.143 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting.
Page 637 RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (29) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 23.144 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 638: Operations Linked By The Elc
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 23.8 Operations Linked by the ELC 23.8.1 Event Signal Output to the ELC The MTU is capable of operation linked with another module set in advance when its interrupt request signal is used as an event signal by the event link controller (ELC).
Page 639: Notes On Mtu By Event Signal Reception From The Elc
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (3) Counter Restart Operation The MTU is selected the count start operation when using the ELOPA and ELOPB registers setting of the ELC. The ELOPA register functions MTU1 to MTU3, and ELOPB register functions MTU4. The TMDR register of the channel set by MTU should be set to the value after reset, 00h.
Page 640: Port Output Enable 2 (Poe2A)
RX23W Group 24. Port Output Enable 2 (POE2a) Port Output Enable 2 (POE2a) The port output enable 2 (POE) module can be used to place the states of the pins for complementary PWM output by the MTU (MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4B, MTIOC4C, and MTIOC4D), and the states of pins for MTU0 (MTIOC0A, MTIOC0B, and MTIOC0C) in the high-impedance in response to changes in the input levels on the POE0#, POE1#, POE3# and POE8# pins, in the output levels on pins for complementary PWM output by the MTU, oscillation stop detection by the clock generation circuit, and changes to register settings (SPOER) or event signal input from the...
Page 641 RX23W Group 24. Port Output Enable 2 (POE2a) POECR1 POECR2 OSTST Oscillation stop detection signal from the clock generation circuit MTIOC3B Output level comparison circuit MTIOC3D MTIOC4A Output level MTIOC4C comparison circuit High-impedance request signal for MTU3 and MTU4 pins MTIOC4B Output level MTIOC4D...
Page 642 RX23W Group 24. Port Output Enable 2 (POE2a) Table 24.2 lists I/O pins to be used by the POE. Table 24.2 POE I/O Pins Pin Name Description POE0#, POE1#, Input Request signals to place the pins for MTU complementary PWM output in high-impedance. POE3# POE8# Input...
Page 643: Register Descriptions
RX23W Group 24. Port Output Enable 2 (POE2a) 24.2 Register Descriptions 24.2.1 Input Level Control/Status Register 1 (ICSR1) Address(es): 0008 8900h POE3F — POE1F POE0F — — — PIE1 POE3M[1:0] — — POE1M[1:0] POE0M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE0M[1:0]...
Page 644 RX23W Group 24. Port Output Enable 2 (POE2a) When low-level sampling has been set by the POE0M[1:0], POE1M[1:0], and POE3M[1:0] bits, writing 0 to the POE0F, POE1F, and POE3F flags requires high-level input on the POE0#, POE1F, and POE3# pins. For details, refer to section 24.3.6, Release from the High-Impedance .
Page 645: Output Level Control/Status Register 1 (Ocsr1)
RX23W Group 24. Port Output Enable 2 (POE2a) 24.2.2 Output Level Control/Status Register 1 (OCSR1) Address(es): 0008 8902h OSF1 — — — — — OCE1 OIE1 — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 646: Input Level Control/Status Register 2 (Icsr2)
RX23W Group 24. Port Output Enable 2 (POE2a) 24.2.3 Input Level Control/Status Register 2 (ICSR2) Address(es): 0008 8908h — — — POE8F — — POE8E PIE2 — — — — — — POE8M[1:0] Value after reset: Symbol Bit Name Description b1, b0 POE8M[1:0] POE8 Mode...
Page 647: Software Port Output Enable Register (Spoer)
RX23W Group 24. Port Output Enable 2 (POE2a) 24.2.4 Software Port Output Enable Register (SPOER) Address(es): 0008 890Ah CH0HI CH34HI — — — — — — Value after reset: Symbol Bit Name Description CH34HIZ MTU3 and MTU4 Output High- 0: Does not place the pins in high-impedance. Impedance Enable 1: Places the pins in high-impedance.
Page 648: Port Output Enable Control Register 1 (Poecr1)
RX23W Group 24. Port Output Enable 2 (POE2a) 24.2.5 Port Output Enable Control Register 1 (POECR1) Address(es): 0008 890Bh — — — — — PE2ZE PE1ZE PE0ZE Value after reset: Symbol Bit Name Description PE0ZE MTIOC0A High-Impedance 0: Does not place the pin in high-impedance. R/W* Enable 1: Places the pin in high-impedance.
Page 649: Port Output Enable Control Register 2 (Poecr2)
RX23W Group 24. Port Output Enable 2 (POE2a) 24.2.6 Port Output Enable Control Register 2 (POECR2) Address(es): 0008 890Ch P1CZE P2CZE P3CZE — — — — — Value after reset: Symbol Bit Name Description b3 to b0 — Reserved These bits are read as 0. The write value should be 0. P3CZEA MTU Port 3 High-Impedance 0: Comparison of output levels does not proceed and the...
Page 650: Input Level Control/Status Register 3 (Icsr3)
RX23W Group 24. Port Output Enable 2 (POE2a) 24.2.7 Input Level Control/Status Register 3 (ICSR3) Address(es): 0008 890Eh OSTST OSTST — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b8 to b0 —...
Page 651: Operation
RX23W Group 24. Port Output Enable 2 (POE2a) 24.3 Operation The target pins for high-impedance control and conditions to place the pins in high-impedance are described below. (1) MTU0 pin (MTIOC0A) When any of the following conditions is satisfied, the pin is placed to the high-impedance state. ...
Page 652 RX23W Group 24. Port Output Enable 2 (POE2a) (5) MTU4 pins (MTIOC4A and MTIOC4C) When any of the following conditions is satisfied, the pins are placed to the high-impedance state.  POE0#, POE1#, and POE3# input level detection When the ICSR1.POE3F, POE1F, or POE0F flag is set to 1 with POECR2.P2CZEA set to 1. ...
Page 653: Input Level Detection Operation
RX23W Group 24. Port Output Enable 2 (POE2a) 24.3.1 Input Level Detection Operation If the input conditions set by the ICSR1 and ICSR2 registers occur on the POE0# to POE3# and POE8# pins, the pins for the MTU complementary PWM output and MTU0 are placed in high-impedance. (1) Falling Edge Detection When a change from a high to low level is input to the POE0#, POE1#, POE3# and POE8# pins, the pins for the MTU complementary PWM output and MTU0 are placed in high-impedance.
Page 654: Output-Level Compare Operation
RX23W Group 24. Port Output Enable 2 (POE2a) (2) Low-Level Detection Figure 24.3 shows the low-level detection operation. When a low level is detected 16 times continuously with the sampling clock selected by the ICSR1 and ICSR2 registers, the detected level is recognized as low, and the pins for the MTU complementary PWM output and MTU0 are placed in high-impedance.
Page 655: High-Impedance Control Using Registers
RX23W Group 24. Port Output Enable 2 (POE2a) 24.3.3 High-Impedance Control Using Registers The high-impedance of the MTU complementary PWM output and MTU0 pins can be directly controlled by writing to the software port output enable register (SPOER). Setting the SPOER.CH34HIZ bit to 1 places the MTU complementary PWM output pins (MTU3 and MTU4) specified by the POECR2 register in the high-impedance.
Page 656: Interrupts
RX23W Group 24. Port Output Enable 2 (POE2a) 24.4 Interrupts The POE issues a request to generate an interrupt when the corresponding condition below is matched during input-level detection, output-level comparison, or oscillation stop by the clock generation circuit. Table 24.4 lists the interrupt sources and their request conditions.
Page 657: Overview
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 16-Bit Timer Pulse Unit (TPUa) This MCU has on-chip 16-bit timer pulse units (TPU) comprising six-channel 16-bit timers. In this section, “PCLK” is used to refer to PCLKB. 25.1 Overview Specifications of the TPU are listed in Table 25.1 . Functions of TPU are listed in Table 25.2 . Figure 25.1 shows a block diagram of TPU.
Page 658 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.2 TPU Functions Item TPU0 TPU1 TPU2 TPU3 TPU4 TPU5 Count clocks PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/64 PCLK/64 PCLK/64 PCLK/64...
Page 659 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) [Interrupt request signals] [Input/output pins] TPU3: TGI3A TPU3: TIOCA3 TGI3B TIOCB3 TGI3C TIOCC3 TGI3D TIOCD3 TCI3V TPU4: TIOCA4 TGI4A TPU4: TIOCB4 TGI4B TPU5: TIOCB5 TCI4V TCI4U TPU5: TGI5A TGI5B TCI5V TCI5U [Clock input] Internal clock: PCLK/1 PCLK/4...
Page 660 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.3 lists the input/output pins of the TPU. Table 25.3 Pin Configuration of TPU Channel Pin Name Description Common TCLKA Input External clock A input pin (TPU1 and TPU5 phase counting mode A phase input) TCLKB Input External clock B input pin (TPU1 and TPU5 phase counting mode B phase input)
Page 661: Register Descriptions
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.2 Register Descriptions 25.2.1 Timer Control Register (TCR) Address(es): TPU0.TCR 0008 8110h, TPU1.TCR 0008 8120h, TPU2.TCR 0008 8130h, TPU3.TCR 0008 8140h, TPU4.TCR 0008 8150h, TPU5.TCR 0008 8160h CCLR[2:0] CKEG[1:0] TPSC[2:0] Value after reset: Symbol Bit Name Description...
Page 662 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.4 Bits TPSC[2:0] (TPU0) Bits TPSC[2:0] Channel Description TPU0 Internal clock: counts on PCLK/1 Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 663 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.7 Bits TPSC[2:0] (TPU3) Bits TPSC[2:0] Channel Description TPU3 Internal clock: counts on PCLK/1 Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock: counts on TCLKA pin input Internal clock: counts on PCLK/1024 Internal clock: counts on PCLK/256 Internal clock: counts on PCLK/4096...
Page 664 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.10 Bits CKEG[1:0] Bits CKEG[1:0] Input Clock Internal Clock External clock Counted at falling edge Counted at rising edge Counted at rising edge Counted at falling edge Counted at both edges Counted at both edges Counted at both edges Counted at both edges...
Page 665: Timer Mode Register (Tmdr)
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.2.2 Timer Mode Register (TMDR) Address(es): TPU0.TMDR 0008 8111h, TPU1.TMDR 0008 8121h, TPU2.TMDR 0008 8131h, TPU3.TMDR 0008 8141h, TPU4.TMDR 0008 8151h, TPU5.TMDR 0008 8161h ICSEL ICSELB MD[3:0] Value after reset: Symbol Bit Name Description b3 to b0 MD[3:0]...
Page 666: Timer I/O Control Register (Tiorh, Tiorl, Tior)
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) ICSELD Bit (TGRD Input Capture Input Select) Selects the input capture input for TPUm.TGRD (m = 3). This function allows measurement of high-level width and period of the input pulse on a TIOCCn input pin. 25.2.3 Timer I/O Control Register (TIORH, TIORL, TIOR) ...
Page 667 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) TPU has two TIORH registers, one for TPU0 and TPU3, and one TIORL register for TPU3, and also has four TIOR registers, one for TPU1, TPU2, TPU4, and TPU5. Thus the TPU has seven timer I/O control registers in total. TIORH, TIORL, and TIOR control registers TGRA, TGRB, TGRC, and TGRD.
Page 668 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.13 TPU0.TIOR Bits IOB[3:0] Description TPU0.TGRB Function TIOCB0 Pin Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output; high output at compare match Initial output is low output;...
Page 669 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.15 TPU2.TIOR Bits IOB[3:0] Description TPU2.TGRB Function TIOCB2 Pin (Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output; high output at compare match Initial output is low output;...
Page 670 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.16 TPU3.TIORH Bits IOA[3:0] Description TPU3.TGRA Function TIOCA3 Pin Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output; high output at compare match Initial output is low output;...
Page 671 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.17 TPU4.TIOR Bits IOA[3:0] Description TPU4.TGRA Function TIOCA4 Pin Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output; high output at compare match Initial output is low output;...
Page 672 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.18 TPU5.TIOR Bits IOB[3:0] Description TPU5.TGRB Function TIOCB5 Pin Function and Related Issue Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output; high output at compare match Initial output is low output;...
Page 673 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.19 TPU3.TIORL Bits IOC[3:0] Description TPU3.TGRC Function TIOCC3 Pin Function and Related Issue Output compare register* Output disabled Initial output is low output; low output at compare match Initial output is low output; high output at compare match Initial output is low output;...
Page 674: Timer Interrupt Enable Register (Tier)
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.2.4 Timer Interrupt Enable Register (TIER) Address(es): TPU0.TIER 0008 8114h, TPU1.TIER 0008 8124h, TPU2.TIER 0008 8134h, TPU3.TIER 0008 8144h, TPU4.TIER 0008 8154h, TPU5.TIER 0008 8164h TTGE — TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Value after reset: Symbol Bit Name...
Page 675: Timer Status Register (Tsr)
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.2.5 Timer Status Register (TSR) Address(es): TPU0.TSR 0008 8115h, TPU1.TSR 0008 8125h, TPU2.TSR 0008 8135h, TPU3.TSR 0008 8145h, TPU4.TSR 0008 8155h, TPU5.TSR 0008 8165h TCFD — TCFU TCFV TGFD TGFC TGFB TGFA Value after reset: Symbol Bit Name...
Page 676 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) TGFA Flag (Input Capture/Output Compare Flag A) This status flag indicates that input capture to TPUm.TGRA or compare match with TPUm.TGRA (m = 0 to 5) has occurred. [Setting conditions]  When TPUm.TGRA holds the value for comparison in output-compare operations, TPUm.TCNT matches TPUm.TGRA.
Page 677 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) TCFV Flag (Overflow Flag) This status flag indicates an overflow of TPUm.TCNT (m = 0 to 5). [Setting condition]  Overflow of the value in TPUm.TCNT (TCNT counted from FFFFh to 0000h). [Clearing condition] ...
Page 678: Timer Counter (Tcnt)
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.2.6 Timer Counter (TCNT) Address(es): TPU0.TCNT 0008 8116h, TPU1.TCNT 0008 8126h, TPU2.TCNT 0008 8136h, TPU3.TCNT 0008 8146h, TPU4.TCNT 0008 8156h, TPU5.TCNT 0008 8166h Value after reset: TPUm.TCNT is a readable/writable counter that counts the internal clock or external events. 25.2.7 Timer General Register A (TGRA), Timer General Register B (TGRB), Timer General Register C (TGRC), Timer General Register D (TGRD)
Page 679: Timer Start Register (Tstr)
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.2.8 Timer Start Register (TSTR) Address(es): TPU.TSTR 0008 8100h — — CST5 CST4 CST3 CST2 CST1 CST0 Value after reset: Symbol Bit Name Description CST0 Counter Start 0 0: TCNT count operation is stopped 1: TCNT performs count operation CST1 Counter Start 1...
Page 680: Timer Synchronous Register (Tsyr)
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.2.9 Timer Synchronous Register (TSYR) Address(es): TPU.TSYR 0008 8101h — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Value after reset: Symbol Bit Name Description SYNC0 Timer Synchronization 0 0: TCNT operates independently (TCNT setting/clearing is unrelated to other channels) SYNC1 Timer Synchronization 1...
Page 681: Noise Filter Control Register (Nfcr)
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.2.10 Noise Filter Control Register (NFCR) Address(es): TPU0.NFCR 0008 8108h, TPU1.NFCR 0008 8109h, TPU2.NFCR 0008 810Ah, TPU3.NFCR 0008 810Bh, TPU4.NFCR 0008 810Ch, TPU5.NFCR 0008 810Dh — — NFCS[1:0] NFDEN NFCEN NFBEN NFAEN Value after reset: Symbol Bit Name...
Page 682 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) NFDEN Bit (Noise Filter Enable D) This bit disables or enables the noise filter for the TIOCDm pin (m = 3). Since unexpected edges may be internally generated when the value of NFDEN is changed, select the output compare function in the timer I/O control register before changing the NFDEN value.
Page 683: Operation
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.3 Operation 25.3.1 Basic Functions Each channel has a TPUm.TCNT and a TPUm.TGRy register (y = A to D). TCNT is a 16-bit up-counter, which can function as a free-running counter, periodic counter, or event counter. TGRy can be used as an input capture register or output compare register.
Page 684 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (b) Free-running count operation and periodic count operation Immediately after a reset, TPUm.TCNT are all set as free-running counters. When the relevant bit in TPU.TSTR is set to 1, the corresponding TCNT starts up-count operation as a free-running counter. When TCNT overflows (changes from FFFFh to 0000h), the TPU requests an interrupt.
Page 685 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (2) Waveform Output by Compare Match The TPU can perform low, high, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 25.5 shows an example of the setting procedure for waveform output by a compare match.
Page 686 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Figure 25.7 shows an example of toggle output. In this example, TPUm.TCNT has been set as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match FFFFn...
Page 687 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (a) Example of setting procedure for input capture operation Figure 25.8 shows an example of the setting procedure for input capture operation. Input selection [1] Enable or disable the noise filter by setting the NFAEN to NFDEN bits in NFCR while an output compare function is set for the corresponding pins with TIOR or a mode other than normal operation...
Page 688 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (b) Example of input capture operation Figure 25.9 shows an example of input capture operation when the noise filter is stopped. In this example, both rising and falling edges have been selected as the TIOCAn pin input capture input edge, the falling edge has been selected as the TIOCBn pin input capture input edge, and counter clearing by TPUm.TGRB input capture has been set for TPUm.TCNT.
Page 689: Synchronous Operation
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.3.2 Synchronous Operation In synchronous operation, the values in multiple TPUm.TCNT can be rewritten simultaneously (synchronous setting). Also, multiple TCNT can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TPUm.TCR.
Page 690 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (2) Example of Synchronous Operation Figure 25.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been set for TPU0 to TPU2, TPU0.TGRA compare match has been set as the TPU0 counter clearing source, and synchronous clearing has been set for the TPU1 and TPU2 counter clearing source.
Page 691: Buffer Operation
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.3.3 Buffer Operation Buffer operation, provided for TPU0 and TPU3, enables TPUm.TGRC and TPUm.TGRD to be used as buffer registers. Buffer operation differs depending on whether TPUm.TGRy has been set as an input capture register or a compare match register.
Page 692 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (1) Example of Buffer Operation Setting Procedure Figure 25.14 shows an example of the buffer operation setting procedure. Buffer operation [1] Set TGRy as an input capture register or output compare register by TIOR (y = A to D). Select TGRy function [2] Set TGRy for buffer operation with bits BFA and BFB in TMDR.
Page 693 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (b) When TPUm.TGRy is an input capture register Figure 25.16 shows an operation example in which TPUm.TGRA has been set as an input capture register, and buffer operation has been set for the TGRA register and TPUm.TGRC. Counter clearing by TGRA input capture has been set for TPUm.TCNT, and both rising and falling edges have been selected as the TIOCAn pin input capture input edge.
Page 694: Cascaded Operation
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.3.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the TPU1 (TPU4) count clock at overflow/underflow of TPU2.TCNT (TPU5.TCNT) as set by the TPSC[2:0] bits in TPU1.TCR (TPSC[2:0] bits in TPU4.TCR).
Page 695 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (2) Examples of Cascaded Operation Figure 25.18 shows the operation when counting upon TPU2.TCNT overflow/underflow has been set for TPU1.TCNT, TPU1.TGRB and TPU2.TGRB have been set as input capture registers, and the rising edge of the TIOCB1 and TIOCB2 pins has been selected.
Page 696: Pwm Modes
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.3.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. low, high, or toggle output can be selected as the output level in response to compare match of each TPUm.TGRy. Settings of TGRy registers can output a PWM waveform in the range of 0% to 100% duty cycle.
Page 697 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) The correspondence between PWM output pins and registers is listed in Table 25.22 . Table 25.22 PWM Output Registers and Output Pins Output Pin Channel Register PWM Mode 1 PWM Mode 2 TPU0 TPU0.TGRA No pin is assigned for this output.
Page 698 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (1) Example of PWM Mode Setting Procedure Figure 25.20 shows an example of the PWM mode setting procedure. PWM mode [1] Select the count clock with the TPSC[2:0] bits in TCR. At the same time, select the input clock Select count clock edge with the CKEG[1:0] bits in TCR.
Page 699 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (2) Examples of PWM Mode Operation Figure 25.21 shows an example of PWM mode 1 operation. In this example, TPUm.TGRA compare match is set as the TPUm.TCNT clearing source, low is set for the TGRA initial output value and output value, and high is set as the TPUm.TGRB output value.
Page 700 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Figure 25.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB changed TGRB TGRB changed 0000h Time 0% duty cycle TIOCAn Output does not change when compare matches in cycle register and duty register occur simultaneously.
Page 701: Phase Counting Mode
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.3.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected by the settings for channels 1, 2, 4, and 5, and TPUm.TCNT is incremented/decremented accordingly. When phase counting mode is set, an external clock is selected as the count clock and TCNT operates as an up-/down- counter regardless of the setting of the TPSC[2:0] bits and CKEG[1:0] bits in TPUm.TCR.
Page 702 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (2) Examples of Phase Counting Mode Operation In phase counting mode, TPUm.TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 25.25 shows an example of phase counting mode 1 operation, and Table 25.24 lists the TPUm.TCNT up-/ down-count conditions.
Page 703 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (b) Phase counting mode 2 Figure 25.26 shows an example of phase counting mode 2 operation, and Table 25.25 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Up-count...
Page 704 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Phase counting mode 3 Figure 25.27 shows an example of phase counting mode 3 operation, and Table 25.26 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Up-count...
Page 705 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (d) Phase counting mode 4 Figure 25.28 shows an example of phase counting mode 4 operation, and Table 25.27 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Up-count...
Page 706: Phase Counting Mode Application Example
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.3.6.1 Phase Counting Mode Application Example Figure 25.29 shows an example in which phase counting mode is set for TPU4, and TPU4 is coupled with TPU3 to input servo motor 2-phase encoder pulses in order to detect the position or speed. TPU4 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to the TCLKA and TCLKB pins.
Page 707: Noise Filters
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.3.7 Noise Filters Each pin for use in input capture by TPU is equipped with a noise filter. The noise filter samples the level on the pin three times at the selected sampling interval, conveys the level to the internal circuits if the samples match, and continues to convey that level until the other level is sampled from the pins three times in a row.
Page 708: Interrupt Sources
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.4 Interrupt Sources There are three kinds of TPU interrupt sources: TPUm.TGRy input capture/compare match, TPUm.TCNT overflow, and TPUm.TCNT underflow. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 15, Interrupt Controller (ICUb) .
Page 709: Dtc Activation
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (1) Input Capture/Compare Match Interrupt An interrupt is requested when the TGIEy bit (y = A, B, C, D) in TPUm.TIER is set to 1 by the occurrence of a TPUm.TGRy input capture/compare match on a channel. The TPU has 16 input capture/compare match interrupts, four each for TPU0 and TPU3, and two each for TPU1, TPU2, TPU4, and TPU5.
Page 710: Operation Timing
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.8 Operation Timing 25.8.1 Input/Output Timing (1) TPUm.TCNT Count Timing Figure 25.31 shows TPUm.TCNT count timing in internal clock operation, and Figure 25.32 shows TCNT count timing in external clock operation. PCLK Falling edge Rising edge Falling edge...
Page 711 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TPUm.TCNT and TPUm.TGRy match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TPUm.TIORH, TPUm.TIORL, or TPUm.TIOR is output to the output compare output pin TIOCyn (y = A to D;...
Page 712 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 25.35 shows the timing when counter clearing by compare match occurrence is specified, and Figure 25.36 shows the timing when counter clearing by input capture occurrence is specified. PCLK Compare match signal Counter clear signal...
Page 713 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (5) Buffer Operation Timing Figure 25.37 and Figure 25.38 show the timings in buffer operation. PCLK N + 1 TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 25.37 Buffer Operation Timing (Compare Match) PCLK Input capture signal TCNT...
Page 714: Interrupt Signal Timing
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.8.2 Interrupt Signal Timing (1) Timing of Interrupt Signal Setting on Compare Match Figure 25.39 shows the timing for setting the interrupt signal by compare match occurrence. PCLK TCNT input clock TCNT N + 1 TGRy Compare match signal...
Page 715 RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) (3) Timing of TCImV/TCImU Interrupt Signal Setting Figure 25.41 shows the timing for generating the TCImV interrupt signal by overflow occurrence. Figure 25.42 shows the timing for generating the TCImU interrupt signal by underflow occurrence. PCLK TCNT input clock TCNT (overflow)
Page 716: Usage Notes
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9 Usage Notes 25.9.1 Module Stop Function Setting Operation of the TPU can be disabled or enabled using the module stop control register. The TPU does not operate with the initial setting. Register access is enabled by releasing the module stop state. For details, see section 11, Low Power Consumption .
Page 717: Conflict Between Tpum.tcnt Write And Clear Operations
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.4 Conflict between TPUm.TCNT Write and Clear Operations If the counter clearing signal is generated in a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 25.44 shows the timing in this case. TCNT write by CPU PCLK Counter clear signal...
Page 718: Conflict Between Tpum.tgry Write And Compare Match
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.6 Conflict between TPUm.TGRy Write and Compare Match If a compare match occurs in a TGRy write cycle, the TGRy write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 25.46 shows the timing in this case.
Page 719: Conflict Between Tpum.tgry Read And Input Capture
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.8 Conflict between TPUm.TGRy Read and Input Capture If the input capture signal is generated in a TGRy read cycle, the data that is read will be the data before input capture transfer.
Page 720: Conflict Between Buffer Register Write And Input Capture
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 25.50 shows the timing in this case. Buffer register write by CPU PCLK Input capture signal...
Page 721: Conflict Between Overflow/Underflow And Counter Clearing
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.12 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, TPUm.TCNT is cleared with the generation of the compare match interrupt and an overflow interrupt is generated. Figure 25.51 shows the operation timing when a TPUm.TGRy compare match is specified as the clearing source and FFFFh is set in TGRy.
Page 722: Conflict Between Tpum.tcnt Write And Overflow/Underflow
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.13 Conflict between TPUm.TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in a TCNT write cycle, the TCNT write takes precedence. Figure 25.52 shows the operation timing when there is conflict between TCNT write and overflow. TCNT write by CPU PCLK TCNT write data...
Page 723: Continuous Output Of Compare-Match Pulse Interrupt Signal
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.15 Continuous Output of Compare-Match Pulse Interrupt Signal When TGR is set to 0000h, PCLK/1 is set as the count clock, and compare match is set as the counter clear source, the TCNT remains 0000h and is not updated, and a compare-match pulse interrupt signal is output continuously to form a flat signal level.
Page 724: Continuous Output Of Input-Capture Pulse Interrupt Signal
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.16 Continuous Output of Input-Capture Pulse Interrupt Signal When input-capture signal is set on both edges and when the pulse width of the input-capture input equals to one PCLK cycle detected by internal sampling, input capture is generated continuously on the rising and falling edges. Therefore, an input-capture pulse interrupt signal is output continuously to form a flat signal level.
Page 725: Continuous Output Of Underflow Pulse Interrupt Signal
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) 25.9.17 Continuous Output of Underflow Pulse Interrupt Signal If two external clock signals' same direction edges to be phase counted are generated within two PCLK cycles in phase counting mode 1, with TGR being 0000h, and compare match set as the counter clear source, the TCNT remains 0000h and is not updated, and a compare-match pulse interrupt signal and an underflow interrupt signal are output continuously to form a flat signal level.
Page 726: Bit Timer (Tmr)
RX23W Group 26. 8-Bit Timer (TMR) 8-Bit Timer (TMR) This MCU has two units (unit 0, unit 1) of an on-chip 8-bit timer (TMR) module that comprise two 8-bit counter channels, totaling four channels. The 8-bit timer module can be used to count external events and also be used as a multi- function timer in a variety of applications, such as generation of counter reset signal, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers.
Page 727 RX23W Group 26. 8-Bit Timer (TMR) Table 26.2 TMR Functions Item Unit 0 Unit 1 Counter mode 8 Bits 16 Bits 8 Bits 16 Bits Channel TMR0 TMR1 TMR0 + TMR1 TMR2 TMR3 TMR2 + TMR3 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1...
Page 728 RX23W Group 26. 8-Bit Timer (TMR) Internal clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Count clock 1 Count clock 0 TMCI0 Clock select TMCI1 TCORA TCORA Compare match A1 Compare match A0 Comparator A0 Comparator A1 To SCI TMO0 Overflow 1 TMO1 Overflow 0...
Page 729 RX23W Group 26. 8-Bit Timer (TMR) Internal clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Count clock 3 Count clock 2 TMCI2 Clock select TMCI3 TCORA TCORA Compare match A3 Compare match A2 Comparator A2 Comparator A3 TMO2 Overflow 3 TCNT TCNT Overflow 2...
Page 730 RX23W Group 26. 8-Bit Timer (TMR) Table 26.3 lists the I/O pins of the TMR. Table 26.3 Pin Configuration of TMR Unit Channel Pin Name Description TMR0 TMO0 Output Outputs compare match TMCI0 Input Inputs external count clock TMR1 TMO1 Output Outputs compare match TMCI1...
Page 731: Register Descriptions
RX23W Group 26. 8-Bit Timer (TMR) 26.2 Register Descriptions Table 26.4 Register Allocation for 16-Bit Access Address Register Upper 8 Bits Lower 8 Bits 0008 8208h TMR01.TCNT TMR0.TCNT TMR1.TCNT 0008 8204h TMR01.TCORA TMR0.TCORA TMR1.TCORA 0008 8206h TMR01.TCORB TMR0.TCORB TMR1.TCORB 0008 820Ah TMR01.TCCR TMR0.TCCR TMR1.TCCR...
Page 732: Time Constant Register A (Tcora)
RX23W Group 26. 8-Bit Timer (TMR) 26.2.2 Time Constant Register A (TCORA) Address(es): TMR0.TCORA 0008 8204h, TMR1.TCORA 0008 8205h, TMR2.TCORA 0008 8214h, TMR3.TCORA 0008 8215h, TMR01.TCORA 0008 8204h, TMR23.TCORA 0008 8214h TMR01.TCORA (TMR23.TCORA) TMR0.TCORA (TMR2.TCORA) TMR1.TCORA (TMR3.TCORA) Value after reset: TCORA is an 8-bit readable/writable register.
Page 733: Timer Control Register (Tcr)
RX23W Group 26. 8-Bit Timer (TMR) 26.2.4 Timer Control Register (TCR) Address(es): TMR0.TCR 0008 8200h, TMR1.TCR 0008 8201h, TMR2.TCR 0008 8210h, TMR3.TCR 0008 8211h CMIEB CMIEA OVIE CCLR[1:0] — — — Value after reset: Symbol Bit Name Description b2 to b0 —...
Page 734: Timer Counter Control Register (Tccr)
RX23W Group 26. 8-Bit Timer (TMR) 26.2.5 Timer Counter Control Register (TCCR) Address(es): TMR0.TCCR 0008 820Ah, TMR1.TCCR 0008 820Bh, TMR2.TCCR 0008 821Ah, TMR3.TCCR 0008 821Bh, TMR01.TCCR 0008 820Ah, TMR23.TCCR 0008 821Ah TMRIS — — CSS[1:0] CKS[2:0] Value after reset: Symbol Bit Name Description b2 to b0...
Page 735 RX23W Group 26. 8-Bit Timer (TMR) Table 26.5 Clock Input to TCNT and Count Condition TCCR Register CSS[1:0] CKS[2:0] Channel Description TMR0 — Clock input prohibited (TMR2) Uses external count clock. Counts at rising edge* Uses external count clock. Counts at falling edge* Uses external count clock.
Page 736: Timer Control/Status Register (Tcsr)
RX23W Group 26. 8-Bit Timer (TMR) 26.2.6 Timer Control/Status Register (TCSR)  TMR0.TCSR, TMR2.TCSR Address(es): TMR0.TCSR 0008 8202h, TMR2.TCSR 0008 8212h — — — — OSB[1:0] OSA[1:0] Value after reset: x: Undefined Symbol Bit Name Description b1, b0 OSA[1:0] Output Select A* b1 b0 0 0: No change 0 1: Low is output...
Page 737 RX23W Group 26. 8-Bit Timer (TMR)  TMR1.TCSR Address(es): TMR1.TCSR 0008 8203h — — — — OSB[1:0] OSA[1:0] Value after reset: x: Undefined Symbol Bit Name Description b1, b0 OSA[1:0] Output Select A* b1 b0 0 0: No change 0 1: Low is output 1 0: High is output 1 1: Output is inverted (toggle output) b3, b2...
Page 738: Timer Counter Start Register (Tcstr)
RX23W Group 26. 8-Bit Timer (TMR) 26.2.7 Timer Counter Start Register (TCSTR) Address(es): TMR0.TCSTR 0008 820Ch, TMR2.TCSTR 0008 821Ch — — — — — — — Value after reset: x: Undefined Symbol Bit Name Description Timer Counter Status 0: Count stopped state in response to ELC. 1: Count start state in response to ELC.
Page 739: Operation
RX23W Group 26. 8-Bit Timer (TMR) 26.3 Operation 26.3.1 Pulse Output Figure 26.3 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. 1. Set the TCR.CCLR[1:0] bits to 01b (cleared by compare match A) so that TCNT is cleared at a compare match of TCORA.
Page 740: External Counter Reset Input
RX23W Group 26. 8-Bit Timer (TMR) 26.3.2 External Counter Reset Input Figure 26.4 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRIn input. 1. Set the TCR.CCLR[1:0] bits to 11b (cleared by external counter reset signal) and set the TMRIS bit in TCCR to 1 (cleared when the external counter reset signal is high) so that TCNT is cleared at the high level input of the TMRIn signal.
Page 741: Operation Timing
RX23W Group 26. 8-Bit Timer (TMR) 26.4 Operation Timing 26.4.1 TCNT Count Timing Figure 26.5 shows the count timing of TCNT for internal clock. Figure 26.6 shows the count timing of TCNT for external clock. Note that the external clock pulse width must be at least 1.5 PCLK cycles for increment at a single edge, and at least 2.5 PCLK cycles for increment at both edges.
Page 742: Timing Of Interrupt Signal Output On A Compare Match
RX23W Group 26. 8-Bit Timer (TMR) 26.4.2 Timing of Interrupt Signal Output on a Compare Match A compare match refers to a match between the value of the TCORA or TCORB register and the TCNT, and a compare match interrupt signal is output at this time if the interrupt request is enabled. The compare match is generated in the last cycle in which the values match (at the time at which the value counted by TCNT to produce the match is updated).
Page 743: Timing Of Counter Clear By Compare Match
RX23W Group 26. 8-Bit Timer (TMR) 26.4.4 Timing of Counter Clear by Compare Match TCNT is cleared when compare match A or B occurs, depending on the settings of the TCR.CCLR[1:0] bits. Figure 26.9 shows the timing of this operation. PCLK Compare match signal TCNT...
Page 744: Timing Of Interrupt Signal Output On An Overflow
RX23W Group 26. 8-Bit Timer (TMR) 26.4.6 Timing of Interrupt Signal Output on an Overflow When TCNT overflows (changes from FFh to 00h), an overflow interrupt signal is output if this interrupt request is enabled. Figure 26.12 shows the timing of output of the interrupt signal. For the corresponding interrupt vector number, refer to section 15, Interrupt Controller (ICUb) and Table 26.6 .
Page 745: Operation With Cascaded Connection
RX23W Group 26. 8-Bit Timer (TMR) 26.5 Operation with Cascaded Connection If the CSS[1:0] bits in either TMR0.TCCR or TMR1.TCCR are set to 11b, the TMR of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of TMR0 could be counted by TMR1 (compare match count mode).
Page 746: Interrupt Sources
RX23W Group 26. 8-Bit Timer (TMR) 26.6 Interrupt Sources 26.6.1 Interrupt Sources and DTC Activation There are three interrupt sources for TMRn: CMIAn, CMIBn, and OVIn. Their interrupt sources and priorities are listed in Table 26.6 . It is also possible to activate the DTC by means of CMIAn and CMIBn interrupts. Table 26.6 TMR Interrupt Sources Name...
Page 747: Link Operation By Elc
RX23W Group 26. 8-Bit Timer (TMR) 26.7 Link Operation by ELC 26.7.1 Event Signal Output to ELC The TMR uses the event link controller (ELC) to perform link operation to the previously specified module using the interrupt request signal as the event signal. The TMR outputs compare match A, compare match B, and overflow signals as event signals.
Page 748: Notes On Operating Tmr According To An Event Signal From Elc
RX23W Group 26. 8-Bit Timer (TMR) 26.7.3 Notes on Operating TMR According to an Event Signal from ELC The following describes the notes on operating the TMR using the event link feature. (1) Count Start When the event specified by ELSRn occurs during the write cycle to the TCSTR.TCS bit, the cycle is not completed; setting 1 according to the event occurrence takes priority.
Page 749: Usage Notes
RX23W Group 26. 8-Bit Timer (TMR) 26.8 Usage Notes 26.8.1 Module Stop State Setting Operation of the TMR can be disabled or enabled by using the module stop control registers. The initial setting is for halting of TMR operation. Register access becomes possible after release from the module stop state. For details, refer to section 11, Low Power Consumption .
Page 750: Conflict Between Tcnt Write And Increment
RX23W Group 26. 8-Bit Timer (TMR) 26.8.4 Conflict between TCNT Write and Increment Even if a counting-up signal is generated concurrently with CPU write to TCNT, the counting-up is not performed and the write takes priority as shown in Figure 26.14 . TCNT write by CPU PCLK TCNT count clock...
Page 751: Conflict Between Compare Matches A And B
RX23W Group 26. 8-Bit Timer (TMR) 26.8.6 Conflict between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output methods high for compare match A and compare match B, as listed in Table 26.7 . Table 26.7 Timer Output Priorities Output Setting...
Page 752 RX23W Group 26. 8-Bit Timer (TMR) Table 26.8 Switching of Internal Clocks and TCNT Operation (2/2) Timing to Change the TCCR.CKS[2:0] Bits TCNT Counter Operation Switching from high to low* Clock before switching Clock after switching TCNT count clock TCNT N + 1 N + 2 N + 3...
Page 753: Clock Source Setting With Cascaded Connection
RX23W Group 26. 8-Bit Timer (TMR) 26.8.8 Clock Source Setting with Cascaded Connection If 16-bit counter mode and compare match count mode are specified at the same time, count clocks for TMR0.TCNT and TMR1.TCNT (TMR2.TCNT and TMR3.TCNT) are not generated, and the counter stops. Do not specify 16-bit counter mode and compare match count mode simultaneously.
Page 754: Compare Match Timer (Cmt)
RX23W Group 27. Compare Match Timer (CMT) Compare Match Timer (CMT) This MCU has two on-chip compare match timer (CMT) units (unit 0 and unit 1), each consisting of a two-channel 16-bit timer (i.e., a total of four channels). The CMT has a 16-bit counter, and can generate interrupts at set intervals. In this section, “PCLK”...
Page 755: Register Descriptions
RX23W Group 27. Compare Match Timer (CMT) 27.2 Register Descriptions 27.2.1 Compare Match Timer Start Register 0 (CMSTR0) Address(es): 0008 8000h — — — — — — — — — — — — — — STR1 STR0 Value after reset: Symbol Bit Name Description...
Page 756: Compare Match Timer Control Register (Cmcr)
RX23W Group 27. Compare Match Timer (CMT) 27.2.3 Compare Match Timer Control Register (CMCR) Address(es): CMT0.CMCR 0008 8002h, CMT1.CMCR 0008 8008h, CMT2.CMCR 0008 8012h, CMT3.CMCR 0008 8018h — — — — — — — — — CMIE — — — —...
Page 757: Compare Match Counter (Cmcnt)
RX23W Group 27. Compare Match Timer (CMT) 27.2.4 Compare Match Counter (CMCNT) Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah, CMT2.CMCNT 0008 8014h, CMT3.CMCNT 0008 801Ah Value after reset: The CMCNT counter is a readable/writable up-counter. When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTRm.STRn (m = 0, 1; n = 0 to 3) bit is set to 1, the CMCNT counter starts counting up using the selected clock.
Page 758: Operation
RX23W Group 27. Compare Match Timer (CMT) 27.3 Operation 27.3.1 Periodic Count Operation When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTRm.STRn (m = 0, 1; n = 0 to 3) bit is set to 1, the CMCNT counter starts counting up using the selected clock. When the value in the counter and the value in the register match, a compare match interrupt (CMIn) (n = 0 to 3) is generated.
Page 759: Interrupts
RX23W Group 27. Compare Match Timer (CMT) 27.4 Interrupts 27.4.1 Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt (CMIn) (n = 0 to 3). When a compare match interrupt occurs, the corresponding interrupt request is output. When the interrupt request is used to generate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings.
Page 760: Link Operations By Elc
RX23W Group 27. Compare Match Timer (CMT) 27.5 Link Operations by ELC 27.5.1 Event Signal Output to ELC The CMT uses the event link controller (ELC) to perform link operation to a preset module using the interrupt request signal as the event signal. The CMT outputs the event signal upon a CMT1 compare match. The event signal can be output regardless of the setting of the corresponding interrupt request enable bit (CMTn.CMCR.CMIE).
Page 761: Usage Notes
RX23W Group 27. Compare Match Timer (CMT) 27.6 Usage Notes 27.6.1 Setting the Module Stop Function The CMT can be enabled or disabled using the module stop control register. After a reset, the CMT is in the module stop state. The registers can be accessed by releasing the module stop state. For details, refer to section 11, Low Power Consumption .
Page 762: Realtime Clock (Rtce)
RX23W Group 28. Realtime Clock (RTCe) Realtime Clock (RTCe) In this section, “PCLK” is used to refer to PCLKB. 28.1 Overview The RTC has two types of counting modes: calendar count mode and binary count mode. They are used by switching the register settings.
Page 763 RX23W Group 28. Realtime Clock (RTCe) Internal peripheral bus Realtime clock (RTC) Bus interface To each RCR2 RTCOUT function Time counter 1-Hz/64-Hz output Alarm function Prescaler RSECAR/ RMINAR/ XCIN 128 Hz RSECCNT/ 32.768 kHz Sub-clock 128-Hz generation R64CNT BCNT0AR BCNT1AR BCNT0 oscillator for XCIN...
Page 764: Register Descriptions
RX23W Group 28. Realtime Clock (RTCe) 28.2 Register Descriptions When writing to or reading from RTC registers, do so in accordance with section 28.6.5, Notes When Writing to and Reading from Registers . If the value in an RTC register after a reset is given as x (undefined bits) in the list, it is not initialized by a reset. When RTC enters the reset state or a low power consumption state during counting operations (i.e.
Page 765: Second Counter (Rseccnt)/Binary Counter 0 (Bcnt0)
RX23W Group 28. Realtime Clock (RTCe) 28.2.2 Second Counter (RSECCNT)/Binary Counter 0 (BCNT0) (1) In calendar count mode: Address(es): RTC.RSECCNT 0008 C402h — SEC10[2:0] SEC1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 SEC1[3:0] 1-Second Count Counts from 0 to 9 every second.
Page 766: Minute Counter (Rmincnt)/Binary Counter 1 (Bcnt1)
RX23W Group 28. Realtime Clock (RTCe) 28.2.3 Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1) (1) In calendar count mode: Address(es): RTC.RMINCNT 0008 C404h — MIN10[2:0] MIN1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MIN1[3:0] 1-Minute Count Counts from 0 to 9 every minute.
Page 767: Hour Counter (Rhrcnt)/Binary Counter 2 (Bcnt2)
RX23W Group 28. Realtime Clock (RTCe) 28.2.4 Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2) (1) In calendar count mode: Address(es): RTC.RHRCNT 0008 C406h — HR10[1:0] HR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 HR1[3:0] 1-Hour Count Counts from 0 to 9 once per hour.
Page 768: Day-Of-Week Counter (Rwkcnt)/Binary Counter 3 (Bcnt3)
RX23W Group 28. Realtime Clock (RTCe) 28.2.5 Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3) (1) In calendar count mode: Address(es): RTC.RWKCNT 0008 C408h — — — — — DAYW[2:0] Value after reset: x: Undefined Symbol Bit Name Description b2 to b0 DAYW[2:0] Day-of-Week Counting 0 0 0: Sunday...
Page 769: Date Counter (Rdaycnt)
RX23W Group 28. Realtime Clock (RTCe) 28.2.6 Date Counter (RDAYCNT) Address(es): RTC.RDAYCNT 0008 C40Ah — — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 DATE1[3:0] 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place.
Page 770: Month Counter (Rmoncnt)
RX23W Group 28. Realtime Clock (RTCe) 28.2.7 Month Counter (RMONCNT) Address(es): RTC.RMONCNT 0008 C40Ch — — — MON10 MON1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MON1[3:0] 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place.
Page 771: Year Counter (Ryrcnt)
RX23W Group 28. Realtime Clock (RTCe) 28.2.8 Year Counter (RYRCNT) Address(es): RTC.RYRCNT 0008 C40Eh — — — — — — — — YR10[3:0] YR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 YR1[3:0] 1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place.
Page 772: Second Alarm Register (Rsecar)/Binary Counter 0 Alarm Register (Bcnt0Ar)
RX23W Group 28. Realtime Clock (RTCe) 28.2.9 Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register (BCNT0AR) (1) In calendar count mode: Address(es): RTC.RSECAR 0008 C410h SEC10[2:0] SEC1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 SEC1[3:0] 1 Second Value for the ones place of seconds b6 to b4...
Page 773: Minute Alarm Register (Rminar)/Binary Counter 1 Alarm Register (Bcnt1Ar)
RX23W Group 28. Realtime Clock (RTCe) 28.2.10 Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR) (1) In calendar count mode: Address(es): RTC.RMINAR 0008 C412h MIN10[2:0] MIN1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MIN1[3:0] 1 Minute Value for the ones place of minutes b6 to b4...
Page 774: Hour Alarm Register (Rhrar)/Binary Counter 2 Alarm Register (Bcnt2Ar)
RX23W Group 28. Realtime Clock (RTCe) 28.2.11 Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register (BCNT2AR) (1) In calendar count mode: Address(es): RTC.RHRAR 0008 C414h HR10[1:0] HR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 HR1[3:0] 1 Hour Value for the ones place of hours b5, b4...
Page 775: Day-Of-Week Alarm Register (Rwkar)/Binary Counter 3 Alarm Register (Bcnt3Ar)
RX23W Group 28. Realtime Clock (RTCe) 28.2.12 Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register (BCNT3AR) (1) In calendar count mode: Address(es): RTC.RWKAR 0008 C416h — — — — DAYW[2:0] Value after reset: x: Undefined Symbol Bit Name Description b2 to b0 DAYW[2:0] Day-of-Week Setting 0 0 0: Sunday...
Page 776: Date Alarm Register (Rdayar)/Binary Counter 0 Alarm Enable Register (Bcnt0Aer)
RX23W Group 28. Realtime Clock (RTCe) 28.2.13 Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register (BCNT0AER) (1) In calendar count mode: Address(es): RTC.RDAYAR 0008 C418h — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 DATE1[3:0] 1 Day Value for the ones place of days...
Page 777: Month Alarm Register (Rmonar)/Binary Counter 1 Alarm Enable Register (Bcnt1Aer)
RX23W Group 28. Realtime Clock (RTCe) 28.2.14 Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register (BCNT1AER) (1) In calendar count mode: Address(es): RTC.RMONAR 0008 C41Ah — — MON10 MON1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MON1[3:0] 1 Month Value for the ones place of months...
Page 778: Year Alarm Register (Ryrar)/Binary Counter 2 Alarm Enable Register (Bcnt2Aer)
RX23W Group 28. Realtime Clock (RTCe) 28.2.15 Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register (BCNT2AER) (1) In calendar count mode: Address(es): RTC.RYRAR 0008 C41Ch — — — — — — — — YR10[3:0] YR1[3:0] Value after reset: x: Undefined Symbol Bit Name Description...
Page 779: Year Alarm Enable Register (Ryraren)/Binary Counter 3 Alarm Enable Register (Bcnt3Aer)
RX23W Group 28. Realtime Clock (RTCe) 28.2.16 Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable Register (BCNT3AER) (1) In calendar count mode: Address(es): RTC.RYRAREN 0008 C41Eh — — — — — — — Value after reset: x: Undefined Symbol Bit Name Description b6 to b0...
Page 780: Rtc Control Register 1 (Rcr1)
RX23W Group 28. Realtime Clock (RTCe) 28.2.17 RTC Control Register 1 (RCR1) Address(es): RTC.RCR1 0008 C422h PES[3:0] RTCOS Value after reset: x: Undefined Symbol Bit Name Description Alarm Interrupt Enable 0: An alarm interrupt request is disabled. 1: An alarm interrupt request is enabled. Carry Interrupt Enable 0: A carry interrupt request is disabled.
Page 781: Rtc Control Register 2 (Rcr2)
RX23W Group 28. Realtime Clock (RTCe) 28.2.18 RTC Control Register 2 (RCR2) Address(es): RTC.RCR2 0008 C424h CNTM HR24 AADJP AADJE RTCOE ADJ30 RESET START Value after reset: x: Undefined Symbol Bit Name Description START Start 0: Prescaler and counter are stopped. 1: Prescaler and counter operate normally.
Page 782 RX23W Group 28. Realtime Clock (RTCe) RESET Bit (RTC Software Reset) This bit initializes the prescaler and registers to be reset by RTC software reset. When 1 is written to the RESET bit, the initialization starts in synchronization with the count source. When the initialization is completed, the RESET bit is automatically set to 0.
Page 783: Rtc Control Register 3 (Rcr3)
RX23W Group 28. Realtime Clock (RTCe) 28.2.19 RTC Control Register 3 (RCR3) Address(es): RTC.RCR3 0008 C426h — — — — RTCDV[2:0] RTCEN Value after reset: x: Undefined Symbol Bit Name Description RTCEN Sub-Clock Oscillator Control 0: Sub-clock oscillator is stopped. 1: Sub-clock oscillator is operating.
Page 784: Time Error Adjustment Register (Radj)
RX23W Group 28. Realtime Clock (RTCe) 28.2.20 Time Error Adjustment Register (RADJ) Address(es): RTC.RADJ 0008 C42Eh PMADJ[1:0] ADJ[5:0] Value after reset: x: Undefined Symbol Bit Name Description b5 to b0 ADJ[5:0] Adjustment Value These bits specify the adjustment value from the prescaler. b7, b6 PMADJ[1:0] Plus–Minus...
Page 785: Time Capture Control Register N (Rtccrn) (N = 0, 1)
RX23W Group 28. Realtime Clock (RTCe) 28.2.21 Time Capture Control Register n (RTCCRn) (n = 0, 1) Address(es): RTC.RTCCR0 0008 C440h, RTC.RTCCR1 0008 C442h TCEN — TCNF[1:0] — TCST TCCT[1:0] Value after reset: x: Undefined Symbol Bit Name Description b1, b0 TCCT[1:0] Time Capture Control b1 b0...
Page 786 RX23W Group 28. Realtime Clock (RTCe) TCNF[1:0] Bits (Time Capture Noise Filter Control) These bits control the noise filter of the time capture event input pins (RTCIC0 and RTCIC1). When the noise filter is on, the count source divided by 1 or divided by 32 is selectable. In this case, when the input level on the time capture event input pin matches three consecutive times at the set sampling period, the input level is determined.
Page 787: Second Capture Register N (Rseccpn) (N = 0, 1)/Bcnt0 Capture Register N (Bcnt0Cpn) (N = 0, 1)
RX23W Group 28. Realtime Clock (RTCe) 28.2.22 Second Capture Register n (RSECCPn) (n = 0, 1)/BCNT0 Capture Register n (BCNT0CPn) (n = 0, 1) (1) In calendar count mode: Address(es): RTC.RSECCP0 0008 C452h, RTC.RSECCP1 0008 C462h — SEC10[2:0] SEC1[3:0] Value after reset: x: Undefined Symbol Bit Name...
Page 788: Minute Capture Register N (Rmincpn) (N = 0, 1)/Bcnt1 Capture Register N (Bcnt1Cpn) (N = 0, 1)
RX23W Group 28. Realtime Clock (RTCe) 28.2.23 Minute Capture Register n (RMINCPn) (n = 0, 1)/BCNT1 Capture Register n (BCNT1CPn) (n = 0, 1) (1) In calendar count mode: Address(es): RTC.RMINCP0 0008 C454h, RTC.RMINCP1 0008 C464h — MIN10[2:0] MIN1[3:0] Value after reset: x: Undefined Symbol Bit Name...
Page 789: Hour Capture Register N (Rhrcpn) (N = 0, 1)/Bcnt2 Capture Register N (Bcnt2Cpn) (N = 0, 1)
RX23W Group 28. Realtime Clock (RTCe) 28.2.24 Hour Capture Register n (RHRCPn) (n = 0, 1)/BCNT2 Capture Register n (BCNT2CPn) (n = 0, 1) (1) In calendar count mode: Address(es): RTC.RHRCP0 0008 C456h, RTC.RHRCP1 0008 C466h — HR10[1:0] HR1[3:0] Value after reset: x: Undefined Symbol Bit Name...
Page 790: Date Capture Register N (Rdaycpn) (N = 0, 1)/Bcnt3 Capture Register N (Bcnt3Cpn) (N = 0, 1)
RX23W Group 28. Realtime Clock (RTCe) 28.2.25 Date Capture Register n (RDAYCPn) (n = 0, 1)/BCNT3 Capture Register n (BCNT3CPn) (n = 0, 1) (1) In calendar count mode: Address(es): RTC.RDAYCP0 0008 C45Ah, RTC.RDAYCP1 0008 C46Ah — — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol...
Page 791: Month Capture Register N (Rmoncpn) (N = 0, 1)
RX23W Group 28. Realtime Clock (RTCe) 28.2.26 Month Capture Register n (RMONCPn) (n = 0, 1) Address(es): RTC.RMONCP0 0008 C45Ch, RTC.RMONCP1 0008 C46Ch — — — MON10 MON1[3:0] Value after reset: x: Undefined Symbol Bit Name Description b3 to b0 MON1[3:0] 1-Month Capture Capture value for the ones place of months...
Page 792: Operation
RX23W Group 28. Realtime Clock (RTCe) 28.3 Operation 28.3.1 Outline of Initial Settings of Registers after Power On After the power is turned on, the initial settings for the clock setting, count mode setting, time error adjustment, time setting, alarm, interrupt, and time capture control register should be performed. Power on Clock supply setting and count mode setting Clock and count mode settings...
Page 793: Clock And Count Mode Setting Procedure
RX23W Group 28. Realtime Clock (RTCe) 28.3.2 Clock and Count Mode Setting Procedure Figure 28.3 shows how to set the clock and the count mode. Set the sub-clock oscillator Set the RCR3 register Supply 6 clocks of the count source Set the START bit to 0 Wait for the RCR2.START bit to become 0 START = 0...
Page 794: Setting The Time
RX23W Group 28. Realtime Clock (RTCe) 28.3.3 Setting the Time Figure 28.4 shows how to set the time. Set the START bit to 0 Write 0 to the RCR2.START bit Wait for the RCR2.START bit to become 0 START = 0 Execute an RTC software reset Write 1 to the RCR2.RESET bit* Wait for the RCR2.RESET bit to become 0...
Page 795: Reading 64-Hz Counter And Time
RX23W Group 28. Realtime Clock (RTCe) 28.3.5 Reading 64-Hz Counter and Time Figure 28.6 shows how to read the 64-Hz counter and time. (a) To read the time without using interrupt Write 0 to the ICU.IERm.IENj bit corresponding to Disable a carry interrupt request on ICU side the CUP interrupt Enable a carry interrupt request on RTC side Write 1 to the RCR1.CIE bit...
Page 796: Alarm Function
RX23W Group 28. Realtime Clock (RTCe) 28.3.6 Alarm Function Figure 28.7 shows how to use the alarm function. Check if the clock is operationg Confirm that the RCR2.START bit is 1 (the clock is operating) Disable an alarm interrupt request on ICU side Write 0 to the ICU.IERm.IENj bit corresponding to the ALM interrupt Set the time of the alarm Set the alarm time and enable the alarm at the same time or later...
Page 797: Procedure For Disabling Alarm Interrupt
RX23W Group 28. Realtime Clock (RTCe) 28.3.7 Procedure for Disabling Alarm Interrupt Figure 28.8 shows the procedure for disabling the enabled alarm interrupt request. An alarm interrupt is enabled Start while the RCR1.AIE bit is 1 Write 0 to the ICU.IERm.IENj bit corresponding to Disable an alarm interrupt request on ICU side the ALM interrupt Disable an alarm interrupt request of RTC side...
Page 798: Adjustment By Software
RX23W Group 28. Realtime Clock (RTCe) [Example 2] Sub-clock running at 32.766 kHz Adjustment procedure: When the sub-clock is running at 32.766 kHz, 1 second elapses every 32,766 clock cycles. The RTC is meant to run at 32,768 clock cycles, so the clock runs slow by two clock cycles every second. The time on the clock is slow by 20 clock cycles every 10 seconds, so adjustment can take the form of setting the clock forward by 20 cycles every 10 seconds.
Page 799: Procedure For Changing The Mode Of Adjustment
RX23W Group 28. Realtime Clock (RTCe) 28.3.8.3 Procedure for Changing the Mode of Adjustment When changing the mode of adjustment, change the value of the AADJE bit in RCR2 after setting the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed). Changing from adjustment by software to automatic adjustment: (1) Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed).
Page 800: Capturing The Time
RX23W Group 28. Realtime Clock (RTCe) 28.3.8.5 Capturing the Time The RTC is capable of storing the month, date, hour, minute and second/binary counters 3 to 0 by detecting an edge of a signal on a time capture event input pin. A noise filter can also be used on a time capture event input pin.
Page 801: Interrupt Sources
RX23W Group 28. Realtime Clock (RTCe) 28.4 Interrupt Sources There are three interrupt sources in the realtime clock. Table 28.3 lists interrupt sources for the RTC. Table 28.3 RTC Interrupt Sources Name Interrupt Sources Alarm interrupt Periodic interrupt Carry interrupt (1) Alarm interrupt (ALM) This interrupt is generated according to the result of comparison between the alarm registers and realtime clock counters (for details, refer to section 28.3.6, Alarm Function ).
Page 802 RX23W Group 28. Realtime Clock (RTCe) (3) Carry interrupt (CUP) This interrupt is generated when a carry to the second counter/binary counter 0 occurred or a carry to the R64CNT counter occurred during read access to the 64-Hz counter. 64 Hz Interrupt generated by the simultaneous R64CNT occurrence of the selected edge of the...
Page 803: Event Link Output
RX23W Group 28. Realtime Clock (RTCe) 28.5 Event Link Output The RTC outputs the following event signals for the event link controller (ELC), and these can be used to initiate operations by other modules selected in advance. (1) Periodic event output The periodic event signal is output at the interval selected from among 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2, 1, and 2 seconds by the setting of the RCR1.PES[3:0] bits.
Page 804: Usage Notes
RX23W Group 28. Realtime Clock (RTCe) 28.6 Usage Notes 28.6.1 Register Writing during Counting The following registers should not be written to during counting (while the RCR2.START bit = 1). RSECCNT/BCNT0, RMINCNT/BCNT1, RHRCNT/BCNT2, RDAYCNT, RWKCNT/BCNT3, RMONCNT, RYRCNT, RCR1.RTCOS, RCR2.RTCOE, RCR2.HR24 The counter must be stopped before writing to any of the above registers.
Page 805: Transitions To Low Power Consumption Modes After Setting Registers
RX23W Group 28. Realtime Clock (RTCe) 28.6.4 Transitions to Low Power Consumption Modes after Setting Registers A transition to a low power consumption state (software standby mode, or battery backup) during writing to or updating of an RTC register might destroy the register’s value. After setting a register, confirm that the setting is in place before initiating a transition to a low power consumption state.
Page 806: Initialization Procedure When The Realtime Clock Is Not To Be Used
RX23W Group 28. Realtime Clock (RTCe) 28.6.7 Initialization Procedure When the Realtime Clock is Not to be Used Registers in the RTC are not initialized by a reset. Accordingly, depending on the initial state, the generation of an unintentional interrupt request or operation of the counter may lead to increased power consumption. For products that do not require a realtime clock, initialize the registers by following the initialization procedure shown in Figure 28.14 .
Page 807: Low-Power Timer (Lpt)
RX23W Group 29. Low-Power Timer (LPT) Low-Power Timer (LPT) 29.1 Overview This MCU integrates a low-power timer (LPT) that consists of a single-channel 16-bit timer. The LPT uses a sub-clock or IWDT-dedicated clock as the clock source, and can continue counting operation even in software standby mode. A compare match signal can be used to return from software standby mode to normal operating mode.
Page 808: Register Descriptions
RX23W Group 29. Low-Power Timer (LPT) 29.2 Register Descriptions 29.2.1 Low-Power Timer Control Register 1 (LPTCR1) Address(es): LPT.LPTCR1 0008 00B0h LPCMR LPCNT — — — LPCNTPSSEL[2:0] CKSEL Value after reset: Symbol Bit Name Description b2 to b0 LPCNTPSSEL[2:0] Clock Division Ratio Select 0 0 1: Divided by 2 0 1 0: Divided by 4 0 1 1: Divided by 8...
Page 809 RX23W Group 29. Low-Power Timer (LPT) LPCMRE0 Bit (Compare Match 0 Enable) This bit enables or disables low-power timer compare match 0. When the low-power timer is put into operation and the MCU makes a transition to software standby mode while this bit and the LPWUCR.LPWKUPEN bit are set to 1 (wakeup from software standby mode using low-power timer is enabled), the MCU returns from software standby mode to normal operating mode through the event link controller (ELC) when the value of the low-power timer counter and the setting of the LPCMR0 register matches.
Page 810: Low-Power Timer Control Register 2 (Lptcr2)
RX23W Group 29. Low-Power Timer (LPT) 29.2.2 Low-Power Timer Control Register 2 (LPTCR2) Address(es): LPT.LPTCR2 0008 00B1h LPCNT — — — — — — — Value after reset: Symbol Bit Name Description LPCNTSTP Clock Supply Control 0: Clock is supplied to the low-power timer 1: Supply of clock to the low-power timer is stopped b7 to b1 —...
Page 811: Low-Power Timer Control Register 3 (Lptcr3)
RX23W Group 29. Low-Power Timer (LPT) 29.2.3 Low-Power Timer Control Register 3 (LPTCR3) Address(es): LPT.LPTCR3 0008 00B2h LPCNT LPCNT — — — — — — Value after reset: Symbol Bit Name Description LPCNTEN Low-Power Timer Counter 0: Low-power timer counter stops Operation Control 1: Low-power timer counter operates ...
Page 812: Low-Power Timer Period Setting Register (Lptprd)
RX23W Group 29. Low-Power Timer (LPT) 29.2.4 Low-Power Timer Period Setting Register (LPTPRD) Address(es): LPT.LPTPRD 0008 00B4h LPCNTPRD[15:0] Value after reset: Symbol Bit Name Description b15 to b0 LPCNTPRD[15:0] Low-Power Timer Period Set the period of the low-power timer. Setting Setting range: 0001h to FFFFh Note: Set the PRCR.PRC2 bit to 1 (write enabled) before rewriting this register.
Page 813 RX23W Group 29. Low-Power Timer (LPT) Table 29.3 Example of Low-Power Timer Period Settings for Sub-Clock Division Divided by 2 Divided by 4 Divided by 8 Divided by 16 Divided by 32 ratio Target Actual Actual Actual Actual Actual period period Error period...
Page 814: Low-Power Timer Compare Register 0 (Lpcmr0)
RX23W Group 29. Low-Power Timer (LPT) 29.2.5 Low-Power Timer Compare Register 0 (LPCMR0) Address(es): LPT.LPCMR0 0008 00B8h LPCMR0[15:0] Value after reset: Symbol Bit Name Description b15 to b0 LPCMR0[15:0] Low-Power Timer Compare 0 Set the value of compare match 0 for comparison with the low- power timer counter.
Page 815: Low-Power Timer Standby Wakeup Enable Register (Lpwucr)
RX23W Group 29. Low-Power Timer (LPT) 29.2.6 Low-Power Timer Standby Wakeup Enable Register (LPWUCR) Address(es): LPT.LPWUCR 0008 00BCh LPWKU — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b14 to b0 —...
Page 816: Operation
RX23W Group 29. Low-Power Timer (LPT) 29.3 Operation 29.3.1 Periodic Counting Operation The low-power timer is a 16-bit up-counter that operates regardless of the MCU operating mode * When the LPTCR3.LPCNTEN bit is set to 1 (low-power timer counter operates) after setting the LPTCR1.LPCNTPSSEL[2:0] bits to select the division ratio, the LPTCR1.LPCNTCKSEL bit to select the clock source, and the LPTCR2.LPCNTSTP bit to 0 (clock is supplied to the low-power timer), the low-power timer counter starts counting with the selected clock.
Page 817 RX23W Group 29. Low-Power Timer (LPT) Start of initialization • Refer to section 15, Interrupt Controller (ICUb) for details Set the interrupt controller on the corresponding interrupt vector number. • ELOPC.LPTMD[1:0] bits: Output the compare match event • ELSR8 register: Specify the LPT compare match event Set the ELC signal •...
Page 818: Count Timing Of Low-Power Timer Counter
RX23W Group 29. Low-Power Timer (LPT) 29.3.2 Count Timing of Low-Power Timer Counter The LPTCR1.LPCNTPSSEL[2:0] bits are used to select the counter clock to be input to the low-power timer counter from among five clocks derived from dividing the clock source selected by the LPTCR1.LPCNTCKSEL bit by 2 to 32, respectively.
Page 819: Wakeup From Software Standby Mode By An Interrupt Through The Event Link Controller (Elc)
RX23W Group 29. Low-Power Timer (LPT) 29.4 Wakeup from Software Standby Mode by an Interrupt through the Event Link Controller (ELC) The low-power timer generates an event signal upon LPT compare match 0 to the event link controller (ELC) only in software standby mode.
Page 820: Watchdog Timer (Wdta)
RX23W Group 30. Watchdog Timer (WDTA) Watchdog Timer (WDTA) The watchdog timer (WDT) is a 14-bit down-counter. It can be used to reset this MCU when the counter underflows because its value cannot be refreshed due to the system being out of control. In addition, a non-maskable interrupt can be generated by an underflow.
Page 821: Register Descriptions
RX23W Group 30. Watchdog Timer (WDTA) 30.2 Register Descriptions 30.2.1 WDT Refresh Register (WDTRR) Address(es): 0008 8020h Value after reset: Description b7 to b0 The down-counter is refreshed by writing 00h and then writing FFh to this register WDTRR refreshes the down-counter of the WDT. The down-counter of the WDT is refreshed by writing 00h and then writing FFh to WDTRR (refresh operation) within the refresh-permitted period.
Page 822: Wdt Control Register (Wdtcr)
RX23W Group 30. Watchdog Timer (WDTA) 30.2.2 WDT Control Register (WDTCR) Address(es): 0008 8022h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 TOPS[1:0] Timeout Period Selection b1 b0 0 0: 1024 cycles (03FFh) 0 1: 4096 cycles (0FFFh) 1 0: 8192 cycles (1FFFh) 1 1: 16384 cycles (3FFFh)
Page 823 RX23W Group 30. Watchdog Timer (WDTA) Table 30.2 Timeout Period Settings CKS[3:0] Bits TOPS[1:0] Bits Timeout Period Clock Division Ratio (Number of Cycles) Cycles of PCLK Clock Divide-by-4 1024 4096 4096 16384 8192 32768 16384 65536 Divide-by-64 1024 65536 4096 262144 8192 524288...
Page 824 RX23W Group 30. Watchdog Timer (WDTA) Table 30.3 lists the counter values for the window start and end positions and Figure 30.2 shows the refresh-permitted period set by the RPSS[1:0], RPES[1:0], and TOPS[1:0] bits. Table 30.3 Relationship between Timeout Period and Window Start and End Counter Values Timeout Period Window Start and End Counter Value TOPS[1:0] Bits...
Page 825: Wdt Status Register (Wdtsr)
RX23W Group 30. Watchdog Timer (WDTA) 30.2.3 WDT Status Register (WDTSR) Address(es): 0008 8024h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit Name Description b13 to b0 CNTVAL[13:0] Down-Counter Value Value counted by the down-counter UNDFF Underflow Flag 0: No underflow occurred R(/W) 1: Underflow occurred REFEF...
Page 826: Wdt Reset Control Register (Wdtrcr)
RX23W Group 30. Watchdog Timer (WDTA) 30.2.4 WDT Reset Control Register (WDTRCR) Address(es): 0008 8026h RSTIR — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0 and cannot be modified. RSTIRQS Reset Interrupt Request Selection 0: Non-maskable interrupt request output is enabled...
Page 827: Operation
RX23W Group 30. Watchdog Timer (WDTA) 30.3 Operation 30.3.1 Count Operation in Each Start Mode The WDT has two start modes: auto-start mode, in which counting automatically starts after a reset is released, and register start mode, in which counting is started by refresh operation (writing to the register). In auto-start mode, counting automatically starts after a reset is released in accordance with the settings in option function select register 0 (OFS0) in the ROM.
Page 828 RX23W Group 30. Watchdog Timer (WDTA) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin WDTCR register (1) Initial value Writing to the Writing to the Writing to the (2) Set value register is invalid. register is valid.
Page 829: Auto-Start Mode
RX23W Group 30. Watchdog Timer (WDTA) 30.3.1.2 Auto-Start Mode When the WDTSTRT bit in option function select register 0 (OFS0) is 0, auto-start mode is selected, the WDTCR and WDTRCR registers are disabled, and the settings in the OFS0 register are enabled. Within the reset state, the setting values (clock division ratio, window start and end positions, timeout period, and reset output or interrupt request) of the OFS0 register are set in the WDT registers.
Page 830 RX23W Group 30. Watchdog Timer (WDTA) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin Refresh the counter Active : H Counting starts Counting starts Counting starts Counting starts Underflow Refresh error Refresh error Status flag REFEF flag cleared Active: High...
Page 831: Control Over Writing To The Wdtcr And Wdtrcr Registers
RX23W Group 30. Watchdog Timer (WDTA) 30.3.2 Control over Writing to the WDTCR and WDTRCR Registers Writing to the WDTCR or WDTRCR register is only possible once between the release from the reset state and the first refresh operation. After a refresh operation (counting starts) or by writing to the WDTCR or WDTRCR register, the protection signal in the WDT becomes 1 to protect the WDTCR and WDTRCR registers against subsequent attempts at writing.
Page 832: Reset Output
RX23W Group 30. Watchdog Timer (WDTA) After FFh is written to the WDTRR register, refreshing the down-counter requires up to four cycles of the signal for counting. Therefore, writing FFh to the WDTRR register should be completed four-count cycles before the down- counter underflows.
Page 833: Reading The Down-Counter Value
RX23W Group 30. Watchdog Timer (WDTA) 30.3.6 Reading the Down-Counter Value The WDT stores the counter value in the WDTSR.CNTVAL[13:0] bits. Thus, the counter value can be checked through the WDTSR.CNTVAL[13:0] bits. Figure 30.7 shows the processing for reading the WDT down-counter value when the clock division ratio = PCLK/64. Peripheral module clock (PCLK) Refreshing...
Page 834: Independent Watchdog Timer (Iwdta)
RX23W Group 31. Independent Watchdog Timer (IWDTa) Independent Watchdog Timer (IWDTa) In this section, “PCLK” is used to refer to PCLKB. 31.1 Overview The independent watchdog timer (IWDT) can be used to detect programs being out of control. The user can detect when a program runs out of control if an underflow occurs, by creating a program that refreshes the IWDT counter before it underflows.
Page 835 RX23W Group 31. Independent Watchdog Timer (IWDTa) To use the IWDT, the IWDT-dedicated clock (IWDTCLK) should be supplied so that the IWDT operates even if the peripheral module clock (PCLK) stops. The bus interface and registers operate with PCLK, and the 14-bit counter and control circuits operate with IWDTCLK.
Page 836: Register Descriptions
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.2 Register Descriptions 31.2.1 IWDT Refresh Register (IWDTRR) Address(es): IWDT.IWDTRR 0008 8030h Value after reset: Description b7 to b0 The counter is refreshed by writing 00h and then writing FFh to this register. The IWDTRR register refreshes the counter of the IWDT.
Page 837: Iwdt Control Register (Iwdtcr)
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.2.2 IWDT Control Register (IWDTCR) Address(es): IWDT.IWDTCR 0008 8032h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit Name Description b1, b0 TOPS[1:0] Timeout Period Select b1 b0 0 0: 128 cycles (007Fh) 0 1: 512 cycles (01FFh) 1 0: 1024 cycles (03FFh)
Page 838 RX23W Group 31. Independent Watchdog Timer (IWDTa) TOPS[1:0] Bits (Timeout Period Select) These bits select the timeout period (period until the counter underflows) from among 128, 512, 1024, or 2048 cycles, taking the divided clock specified by the CKS[3:0] bits as one cycle. After the counter is refreshed, the combination of the CKS[3:0] and TOPS[1:0] bits determines the time (number of IWDTCLK cycles) until the counter underflows.
Page 839 RX23W Group 31. Independent Watchdog Timer (IWDTa) RPES[1:0] Bits (Window End Position Select) These bits select 75%, 50%, 25% or 0% of the count period for the window end position of the counter. The window end position should be a value smaller than the window start position (window start position > window end position). If the window end position is greater than the window start position, only the window start position setting is enabled.
Page 840: Iwdt Status Register (Iwdtsr)
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.2.3 IWDT Status Register (IWDTSR) Address(es): IWDT.IWDTSR 0008 8034h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit Name Description b13 to b0 CNTVAL[13:0] Counter Value Value counted by the counter UNDFF Underflow Flag 0: No underflow occurred R/(W) 1: Underflow occurred...
Page 841: Iwdt Reset Control Register (Iwdtrcr)
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.2.4 IWDT Reset Control Register (IWDTRCR) Address(es): IWDT.IWDTRCR 0008 8036h RSTIR — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0. Writing to these bits has no effect. RSTIRQS Reset Interrupt Request Select 0: Non-maskable interrupt request output is enabled.
Page 842: Iwdt Count Stop Control Register (Iwdtcstpr)
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.2.5 IWDT Count Stop Control Register (IWDTCSTPR) Address(es): IWDT.IWDTCSTPR 0008 8038h SLCST — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0 — Reserved These bits are read as 0. Writing to these bits has no effect. SLCSTP Sleep Mode Count Stop Control 0: Count stop is disabled.
Page 843: Operation
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.3 Operation 31.3.1 Count Operation in Each Start Mode Select the IWDT start mode by setting the IWDTSTRT bit in option function select register 0 (OFS0). When the OFS0.IWDTSTRT bit is 1 (register start mode), the IWDTCR, IWDTRCR, and IWDTCSTPR registers are enabled, and counting is started by refresh operation (writing) to the IWDTRR register.
Page 844 RX23W Group 31. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin IWDTCR register (1) Initial value Writing to the Writing to the Writing to the (2) Set value register is invalid. register is valid.
Page 845: Auto-Start Mode
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.3.1.2 Auto-Start Mode When the IWDTSTRT bit in option function select register 0 (OFS0) is 0, auto-start mode is selected, and the IWDTCR, IWDTRCR, and IWDTCSTPR registers are disabled. Within the reset state, the clock divide ratio, window start and end positions, timeout period, reset output or interrupt request output, and counter stop control at transitions to low power consumption states are set using the values specified in the OFS0 register.
Page 846 RX23W Group 31. Independent Watchdog Timer (IWDTa) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES# pin Refresh the counter (active high) Counting starts Counting starts Counting starts Counting starts Underflow Refresh error Refresh error Status flag cleared REFEF flag Status flag...
Page 847: Control Over Writing To The Iwdtcr, Iwdtrcr, And Iwdtcstpr Registers
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.3.2 Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers Writing to the IWDTCR, IWDTRCR, or IWDTCSTPR register is only possible once between the release from the reset state and the first refresh operation. After a refresh operation (counting starts) or the IWDTCR, IWDTRCR, or IWDTCSTPR register is written to, the protection signal in the IWDT becomes 1 to protect registers IWDTCR, IWDTRCR, and IWDTCSTPR against subsequent attempts at writing.
Page 848: Refresh Operation
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.3.3 Refresh Operation The counter is refreshed and starts operation (counting is started by refreshing) by writing the values 00h and then FFh to the IWDTRR register. If a value other than FFh is written after 00h, the counter is not refreshed. After such invalid writing, correct refreshing is performed by again writing 00h and then FFh to the IWDTRR register.
Page 849 RX23W Group 31. Independent Watchdog Timer (IWDTa) Figure 31.6 shows the IWDT refresh-operation waveforms when PCLK > IWDTCLK and clock divide ratio = IWDTCLK. Peripheral module clock (PCLK) IWDT-dedicated clock (IWDTCLK) Data written to IWDTRR register IWDTRR register write Valid signal (internal signal) IWDTRR register Invalid...
Page 850: Status Flags
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.3.4 Status Flags The IWDTSR.REFEF and IWDTSR.UNDFF flags retain the source of the reset signal output from the IWDT or the source of the interrupt request from the IWDT. Thus, after release from the reset state or interrupt request generation, read the IWDTSR.REFEF and IWDTSR.UNDFF flags to check for the reset or interrupt source.
Page 851: Reading The Counter Value
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.3.7 Reading the Counter Value As the counter in IWDT-dedicated clock (IWDTCLK), the counter value cannot be read directly. The IWDT synchronizes the counter value with the peripheral module clock (PCLK) and stores it in the IWDTSR.CNTVAL[13:0] bits.
Page 852: Correspondence Between Option Function Select Register 0 (Ofs0) And Iwdt Registers
RX23W Group 31. Independent Watchdog Timer (IWDTa) 31.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers Table 31.5 lists the correspondence between option function select register 0 (OFS0) used in auto-start mode and the registers used in register start mode. Do not change the OFS0 register setting during IWDT operation.
Page 853: Usb 2.0 Host/Function Module (Usbc)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) USB 2.0 Host/Function Module (USBc) 32.1 Overview This MCU incorporates a USB 2.0 host/function module. The USB module is a USB controller that is equipped to operate as a host controller or function controller. The module supports full-speed and low-speed transfer as defined in Universal Serial Bus (USB) Specification 2.0.
Page 854 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.1 shows a block diagram of the USB. Battery charging BC control controller LINK core SYS registers registers USB device controller USB0_DP Interrupt USB0_DM controller FIFO buffer controller FIFO USB protocol controller engine Memory...
Page 855: Register Descriptions
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2 Register Descriptions 32.2.1 System Configuration Control Register (SYSCFG) Address(es): 000A 0000h DCFM DRPD DPRPU DMRP — — — — — SCKE — CNEN — — — USBE Value after reset: Symbol Bit Name Description USBE...
Page 856 RX23W Group 32. USB 2.0 Host/Function Module (USBc) DMRPU Bit (D– Line Resistor Control) The DMRPU bit enables or disables pulling up the D– line when the function controller is selected. When the DMRPU bit is set to 1 while the function controller is selected, the bit forces a pull-up of the D– line to notify the USB host of connection as a low-speed device.
Page 857: System Configuration Status Register 0 (Syssts0)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.2 System Configuration Status Register 0 (SYSSTS0) Address(es): 000A 0004h OVCMON[1:0] — — — — — — — HTACT — — — IDMON LNST[1:0] Value after reset: Symbol Bit Name Description b1, b0 LNST[1:0] USB Data Line Status Monitor Refer to Table 32.4.
Page 858: Device State Control Register 0 (Dvstctr0)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.3 Device State Control Register 0 (DVSTCTR0) Address(es): 000A 0008h HNPBT EXICE VBUSE WKUP RWUP USBRS RESU — — — — UACT — RHST[2:0] Value after reset: Symbol Bit Name Description  When the host controller is selected b2 to b0 RHST[2:0] USB Bus Reset Status Flag...
Page 859 RX23W Group 32. USB 2.0 Host/Function Module (USBc) RHST[2:0] Flags (USB Bus Reset Status Flag) The RHST[2:0] flags indicate the status of the USB bus reset. When the host controller is selected, the RHST[2:0] flags indicate 100b after the USBRST bit has been set to 1 by software.
Page 860 RX23W Group 32. USB 2.0 Host/Function Module (USBc) RWUPE Bit (Wakeup Detection Enable) The RWUPE bit enables or disables the downstream port peripheral device to use the remote wakeup function (resume signal output) when the host controller is selected. With this bit set to 1, on detecting the remote wakeup signal, the USB detects the resume signal (K-state for 2.5 μs) from the downstream port device and performs the resume processing (drives the port to the K-state).
Page 861: Cfifo Port Register (Cfifo) D0Fifo Port Register (D0Fifo) D1Fifo Port Register (D1Fifo)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.4 CFIFO Port Register (CFIFO) D0FIFO Port Register (D0FIFO) D1FIFO Port Register (D1FIFO) (1) When the MBW bit is 1 Address(es): CFIFO 000A 0014h, D0FIFO 000A 0018h, D1FIFO 000A 001Ch Value after reset: Symbol Bit Name Description...
Page 862 RX23W Group 32. USB 2.0 Host/Function Module (USBc) FIFO Port Bit Accessing the FIFO port bits allows reading the received data from the FIFO buffer or writing the transmit data to the FIFO buffer. Each FIFO port register can be accessed only while the FRDY flag in each FIFO port control register (CFIFOCTR, D0FIFOCTR, or D1FIFOCTR) is 1.
Page 863: Cfifo Port Select Register (Cfifosel) D0Fifo Port Select Register (D0Fifosel) D1Fifo Port Select Register (D1Fifosel)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.5 CFIFO Port Select Register (CFIFOSEL) D0FIFO Port Select Register (D0FIFOSEL) D1FIFO Port Select Register (D1FIFOSEL)  CFIFOSEL Address(es): 000A 0020h BIGEN RCNT — — — — — — ISEL — CURPIPE[3:0] Value after reset: Symbol Bit Name...
Page 864 RX23W Group 32. USB 2.0 Host/Function Module (USBc) CURPIPE[3:0] Bits (CFIFO Port Access Pipe Specification) The CURPIPE[3:0] bits specify the pipe number using which data is read or written through the CFIFO port. After writing to these bits, read these bits to check that the written value agrees with the read value before proceeding to the next process.
Page 865 RX23W Group 32. USB 2.0 Host/Function Module (USBc)  D0FIFOSEL, D1FIFOSEL Address(es): D0FIFOSEL 000A 0028h, D1FIFOSEL 000A 002Ch BIGEN RCNT REW DCLRM DREQE — — — — — — CURPIPE[3:0] Value after reset: Symbol Bit Name Description b3 to b0 CURPIPE FIFO Port Access Pipe 0 0 0 0: DCP (Default control pipe)
Page 866 RX23W Group 32. USB 2.0 Host/Function Module (USBc) CURPIPE[3:0] Bits (FIFO Port Access Pipe Specification) The CURPIPE[3:0] bits specify the pipe number using which data is read or written through the D0FIFO port or D1FIFO port. After writing to these bits, read these bits to check that the written value agrees with the read value before proceeding to the next process.
Page 867: Cfifo Port Control Register (Cfifoctr) D0Fifo Port Control Register (D0Fifoctr) D1Fifo Port Control Register (D1Fifoctr)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.6 CFIFO Port Control Register (CFIFOCTR) D0FIFO Port Control Register (D0FIFOCTR) D1FIFO Port Control Register (D1FIFOCTR) Address(es): CFIFOCTR 000A 0022h, D0FIFOCTR 000A 002Ah, D1FIFOCTR 000A 002Eh BVAL BCLR FRDY — — — —...
Page 868 RX23W Group 32. USB 2.0 Host/Function Module (USBc) FRDY Flag (FIFO Port Ready Flag) The FRDY flag indicates whether the FIFO port can be accessed by the CPU or DMAC/DTC. In the following cases, the USB sets the FRDY flag to 1 but data cannot be read via the FIFO port because there is no data to be read.
Page 869: Interrupt Enable Register 0 (Intenb0)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.7 Interrupt Enable Register 0 (INTENB0) Address(es): 000A 0030h VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE — — — — — — — — Value after reset: Symbol Bit Name Description b7 to b0 —...
Page 870: Interrupt Enable Register 1 (Intenb1)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.8 Interrupt Enable Register 1 (INTENB1) Address(es): 000A 0032h OVRC DTCHE ATTCH EOFER PDDET BCHGE — — — — — SIGNE SACKE — — — INTE0 Value after reset: Symbol Bit Name Description PDDETINTE0 PDDETINT0 Detection Interrupt Enable...
Page 871: Brdy Interrupt Enable Register (Brdyenb)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.9 BRDY Interrupt Enable Register (BRDYENB) Address(es): 000A 0036h PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B — — — — — — RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE...
Page 872: Nrdy Interrupt Enable Register (Nrdyenb)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.10 NRDY Interrupt Enable Register (NRDYENB) Address(es): 000A 0038h PIPE9N PIPE8N PIPE7N PIPE6N PIPE5N PIPE4N PIPE3N PIPE2N PIPE1N PIPE0N — — — — — — RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE RDYE...
Page 873: Bemp Interrupt Enable Register (Bempenb)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.11 BEMP Interrupt Enable Register (BEMPENB) Address(es): 000A 003Ah PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B — — — — — — EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE EMPE...
Page 874: Sof Output Configuration Register (Sofcfg)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.12 SOF Output Configuration Register (SOFCFG) Address(es): 000A 003Ch TRNEN BRDY EDGES — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b3 to b0 —...
Page 875: Interrupt Status Register 0 (Intsts0)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.13 Interrupt Status Register 0 (INTSTS0) Address(es): 000A 0040h VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ[2:0] VALID CTSQ[2:0] Value after reset: 0/1* 0/1* Symbol Bit Name Description b2 to b0 CTSQ[2:0] Control Transfer Stage Flag 0 0 0: Idle or setup stage...
Page 876 RX23W Group 32. USB 2.0 Host/Function Module (USBc) CTSQ[2:0] Flags (Control Transfer Stage Flag) When the host controller is selected, the read value is invalid. VALID Flag (USB Request Reception Flag) When the host controller is selected, the read value is invalid. DVSQ[2:0] Flags (Device State Flag) The DVSQ[2:0] flags are initialized by a USB bus reset.
Page 877 RX23W Group 32. USB 2.0 Host/Function Module (USBc) DVST Flag (Device State Transition Interrupt Status Flag) When the function controller is selected, the USB updates the DVSQ[2:0] value and sets the DVST flag to 1 on detecting a change in the device state. When a device state transition interrupt is generated, clear the status before the USB detects the next device state transition.
Page 878: Interrupt Status Register 1 (Intsts1)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.14 Interrupt Status Register 1 (INTSTS1) Address(es): 000A 0042h OVRC EOFER PDDET BCHG — DTCH ATTCH — — — — SIGN SACK — — — INT0 Value after reset: Symbol Bit Name Description PDDETINT0 PDDET0 Detection Interrupt Status Flag...
Page 879 RX23W Group 32. USB 2.0 Host/Function Module (USBc) SACK Flag (Setup Transaction Normal Response Interrupt Status Flag) Indicates the status of the setup transaction normal response interrupt when the host controller is selected. The USB detects the SACK interrupt when ACK response is returned from the peripheral device during the setup transactions issued by the USB, and sets the SACK flag to 1.
Page 880 RX23W Group 32. USB 2.0 Host/Function Module (USBc) DTCH Flag (USB Disconnection Detection Interrupt Status Flag) Indicates the status of the USB disconnection detection interrupt when the host controller is selected. The USB detects the DTCH interrupt on detecting USB bus disconnection, and sets the DTCH flag to 1. Here, if the corresponding interrupt enable bit has been set to 1 by software, the USB generates the interrupt.
Page 881: Brdy Interrupt Status Register (Brdysts)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.15 BRDY Interrupt Status Register (BRDYSTS) Address(es): 000A 0046h PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B — — — — — — Value after reset: Symbol Bit Name Description PIPE0BRDY BRDY Interrupt Status Flag for 0: Interrupts are not generated.
Page 882: Nrdy Interrupt Status Register (Nrdysts)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.16 NRDY Interrupt Status Register (NRDYSTS) Address(es): 000A 0048h PIPE9N PIPE8N PIPE7N PIPE6N PIPE5N PIPE4N PIPE3N PIPE2N PIPE1N PIPE0N — — — — — — Value after reset: Symbol Bit Name Description PIPE0NRDY NRDY Interrupt Status Flag for PIPE0 0: Interrupts are not generated.
Page 883: Bemp Interrupt Status Register (Bempsts)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.17 BEMP Interrupt Status Register (BEMPSTS) Address(es): 000A 004Ah PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B — — — — — — Value after reset: Symbol Bit Name Description PIPE0BEMP BEMP Interrupt Status Flag for PIPE0 0: Interrupts are not generated.
Page 884: Frame Number Register (Frmnum)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.18 Frame Number Register (FRMNUM) Address(es): 000A 004Ch OVRN CRCE — — — FRNM[10:0] Value after reset: Symbol Bit Name Description b10 to b0 FRNM[10:0] Frame Number Flag Latest frame number b13 to b11 — Reserved These bits are read as 0.
Page 885: Usb Request Type Register (Usbreq)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.19 USB Request Type Register (USBREQ) Address(es): 000A 0054h BREQUEST[7:0] BMREQUESTTYPE[7:0] Value after reset: Symbol Bit Name Description b7 to b0 BMREQUESTTYPE[7:0] Request Type These bits store the USB request bmRequestType value. b15 to b8 BREQUEST[7:0] Request...
Page 886: Usb Request Value Register (Usbval)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.20 USB Request Value Register (USBVAL) Address(es): 000A 0056h Value after reset: When the function controller is selected, the value of wValue that has been received is stored in the USBVAL register. When the host controller is selected, the value of wValue to be transmitted is set.
Page 887: Usb Request Length Register (Usbleng)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.22 USB Request Length Register (USBLENG) Address(es): 000A 005Ah Value after reset: The USBLENG register stores setup requests for control transfers. When the function controller is selected, the value of wLength that has been received is stored. When the host controller is selected, the value of wLength to be transmitted is set.
Page 888: Dcp Configuration Register (Dcpcfg)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.23 DCP Configuration Register (DCPCFG) Address(es): 000A 005Ch SHTNA — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description b3 to b0 —...
Page 889: Dcp Maximum Packet Size Register (Dcpmaxp)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.24 DCP Maximum Packet Size Register (DCPMAXP) Address(es): 000A 005Eh DEVSEL[3:0] — — — — — MXPS[6:0] Value after reset: Symbol Bit Name Description b6 to b0 MXPS[6:0] Maximum Packet Size* These bits set the maximum amount of data (maximum packet size) in payloads for the DCP.
Page 890: Dcp Control Register (Dcpctr)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.25 DCP Control Register (DCPCTR) Address(es): 000A 0060h SUREQ SQCLR SQSET SQMO BSTS SUREQ — — — — PBUSY — — CCPL PID[1:0] Value after reset: Symbol Bit Name Description b1, b0 PID[1:0] Response PID b1 b0...
Page 891 RX23W Group 32. USB 2.0 Host/Function Module (USBc) The USB modifies the setting of the PID[1:0] bits as follows.  The USB sets PID[1:0] bits to 11b (STALL) on receiving the data of a size exceeding the maximum packet size when the PID[1:0] bits has been set to 01b (BUF) by software.
Page 892 RX23W Group 32. USB 2.0 Host/Function Module (USBc) SQMON Flag (Sequence Toggle Bit Monitor Flag) The SQMON flag indicates the expected value of the sequence toggle bit for the next transaction during the DCP transfer. The USB allows the SQMON flag to toggle upon normal completion of the transaction. However, the SQMON flag is not allowed to toggle when a data PID mismatch occurs during the transfer in the receiving direction.
Page 893: Pipe Window Select Register (Pipesel)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.26 Pipe Window Select Register (PIPESEL) Address(es): 000A 0064h — — — — — — — — — — — — PIPESEL[3:0] Value after reset: Symbol Bit Name Description b3 to b0 PIPESEL[3:0] Pipe Window Select 0 0 0 0: No pipe selected...
Page 894: Pipe Configuration Register (Pipecfg)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.27 Pipe Configuration Register (PIPECFG) Address(es): 000A 0068h SHTNA TYPE[1:0] — — — BFRE DBLB — — — EPNUM[3:0] Value after reset: Symbol Bit Name Description b3 to b0 EPNUM[3:0] Endpoint Number* These bits specify the endpoint number for the selected pipe.
Page 895 RX23W Group 32. USB 2.0 Host/Function Module (USBc) EPNUM[3:0] Bits (Endpoint Number) The EPNUM[3:0] bits specify the endpoint number for the selected pipe. Setting 0000b means an unused pipe. Do not make the settings such that the combination of the settings of the DIR and EPNUM[3:0] bits should be the same for two or more pipes (EPNUM[3:0] bits = 0000b can be set for all of the pipes).
Page 896: Pipe Maximum Packet Size Register (Pipemaxp)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.28 Pipe Maximum Packet Size Register (PIPEMAXP) Address(es): 000A 006Ch DEVSEL[3:0] — — — MXPS[8:0] Value after reset: Symbol Bit Name Description  PIPE1 and PIPE2: b8 to b0 MXPS[8:0] Maximum Packet Size* 1 byte (001h) to 256 bytes (100h) ...
Page 897: Pipe Cycle Control Register (Pipeperi)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.29 Pipe Cycle Control Register (PIPEPERI) Address(es): 000A 006Eh — — — IFIS — — — — — — — — — IITV[2:0] Value after reset: Symbol Bit Name Description b2 to b0 IITV[2:0] Interval Error Detection Interval Specify the interval error detection timing for the selected pipe in...
Page 898: Pipen Control Registers (Pipenctr) (N = 1 To 9)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.30 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)  PIPEnCTR (n = 1 to 5) Address(es): PIPE1CTR 000A 0070h, PIPE2CTR 000A 0072h, PIPE3CTR 000A 0074h, PIPE4CTR 000A 0076h, PIPE5CTR 000A 0078h BSTS INBUF ATREP ACLRM SQCLR SQSET SQMO...
Page 899 RX23W Group 32. USB 2.0 Host/Function Module (USBc) PID[1:0] Bits (Response PID) The PID[1:0] bits specify the response type for the next transaction of the relevant pipe. The default setting of the PID[1:0] bits are 00b (NAK). Modify the setting of the PID[1:0] bits to 01b (BUF) to use the relevant pipe for USB transfer.
Page 900 RX23W Group 32. USB 2.0 Host/Function Module (USBc) SQCLR Bit (Sequence Toggle Bit Clear) The SQCLR bit should be set to 1 to clear the expected value (to set DATA0 as the expected value) of the sequence toggle bit for the next transaction of the relevant pipe. Setting the SQCLR bit to 1 through software allows the USB to set DATA0 as the expected value of the sequence toggle bit of the relevant pipe.
Page 901 RX23W Group 32. USB 2.0 Host/Function Module (USBc) BSTS Flag (Buffer Status Flag) Indicates the FIFO buffer status for the relevant pipe. The meaning of the BSTS flag depends on the settings of the PIPECFG.DIR bit, PIPECFG.BFRE bit, and DnFIFOSEL.DCLRM bits as shown in Table 32.9 . Table 32.6 Operation of USB depending on PID[1:0] Bits Setting (When Host Controller is Selected) Transfer Direction...
Page 902 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Table 32.8 Information Cleared by USB by Setting ACLRM = 1 Information Cleared by ACLRM Bit Manipulation Cases in which Clearing Information is Necessary All the information in the FIFO buffer assigned to the relevant When the pipe is to be initialized pipe (both FIFO buffer planes are cleared when double buffer mode is selected)
Page 903 RX23W Group 32. USB 2.0 Host/Function Module (USBc)  PIPEnCTR (n = 6 to 9) Address(es): PIPE6CTR 000A 007Ah, PIPE7CTR 000A 007Ch, PIPE8CTR 000A 007Eh, PIPE9CTR 000A 0080h ACLRM SQCLR SQSET SQMO BSTS — — — — — PBUSY — —...
Page 904 RX23W Group 32. USB 2.0 Host/Function Module (USBc) PID[1:0] Bits (Response PID) The PID[1:0] bits specify the response type for the next transaction of the relevant pipe. The default setting of the PID[1:0] bits are 00b (NAK). Modify the setting of the PID[1:0] bits to 01b (BUF) to use the relevant pipe for USB transfer.
Page 905 RX23W Group 32. USB 2.0 Host/Function Module (USBc) ACLRM Bit (Auto Buffer Clear Mode) Enables or disables auto buffer clear mode for the relevant pipe. To delete the information in the FIFO buffer assigned to the relevant pipe completely, write 1 and then 0 to the ACLRM bit continuously.
Page 906: Pipen Transaction Counter Enable Register (Pipentre) (N = 1 To 5)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.31 PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 1 to 5) Address(es): PIPE1TRE 000A 0090h, PIPE2TRE 000A 0094h, PIPE3TRE 000A 0098h, PIPE4TRE 000A 009Ch, PIPE5TRE 000A 00A0h — — — — —...
Page 907: Pipen Transaction Counter Register (Pipentrn) (N = 1 To 5)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.32 PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5) Address(es): PIPE1TRN 000A 0092h, PIPE2TRN 000A 0096h, PIPE3TRN 000A 009Ah, PIPE4TRN 000A 009Eh, PIPE5TRN 000A 00A2h Value after reset: The PIPEnTRN register retains the setting by a USB bus reset. ...
Page 908: Device Address N Configuration Register (Devaddn) (N = 0 To 5)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.33 Device Address n Configuration Register (DEVADDn) (n = 0 to 5) Address(es): DEVADD0 000A 00D0h, DEVADD1 000A 00D2h, DEVADD2 000A 00D4h, DEVADD3 000A 00D6h, DEVADD4 000A 00D8h, DEVADD5 000A 00DAh — —...
Page 909: Usb Module Control Register (Usbmc)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.34 USB Module Control Register (USBMC) Address(es): 000A 00CCh VDDUS — — — — — — — — — — — — — — — Value after reset: Symbol Bit Name Description VDDUSBE USB Reference Power Supply 0: USB reference power supply circuit off...
Page 910: Bc Control Register 0 (Usbbcctrl0)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.2.35 BC Control Register 0 (USBBCCTRL0) Address(es): 000A 00B0h PDDET CHGDE BATCH VDMS IDPSIN VDPSR IDMSIN IDPSR RPDM — — — — — — — STS0 TSTS0 RCE0 Value after reset: Symbol Bit Name Description RPDME0...
Page 911 RX23W Group 32. USB 2.0 Host/Function Module (USBc) IDPSINKE0 Bit (D+ Pin 0.6 V Input Detection (Comparator and Sink) Control) With this bit set to 1, when the function controller selected, the USB module detects whether VDMSRC (0.6 V) that is output from the function to D–...
Page 912: Operation
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3 Operation 32.3.1 System Control This section describes the register settings that are necessary for initialization of this module and power consumption control. 32.3.1.1 Setting Data to the USB Related Register Setting the SYSCFG.USBE bit to 1 after starting the clock supply to the USB (SYSCFG.SCKE bit = 1) enables and starts USB operation.
Page 913: Example Of Usb External Connection Circuit
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.1.4 Example of USB External Connection Circuit Figure 32.2 shows an example of OTG connection of the USB connector in the self-powered state. The USB controls the signals for enabling a pull-up resistor for the D+ signal and pull-down resistors for the D+ and D– signals.
Page 914 RX23W Group 32. USB 2.0 Host/Function Module (USBc) External connection OTG power supply IC USB0_EXICEN SHDN# USB0_VBUSEN OFFVBUS# USB0_OVRCURA STATUS1 USB0_OVRCURB STATUS2 USB0_ID ID_OUT ID_IN VBUS USB transceiver AB connector VBUS USB0_DP USB0_DM D– : Output impedance : Pull-up resistor : Pull-down resistor Figure 32.2 Sample OTG Connection of USB Connector in Self-Powered State...
Page 915 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.3 shows an example of functional connection of the USB connector in the self-powered state. External connection 100  P16 or PB5 USB0_VBUS 1 M 0.1 µF B connector transceiver VBUS USB0_DP USB0_DM D–...
Page 916 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.4 shows an example of functional connection of the USB connector with Battery Charging Specification Revision 1.2 supported. External connection Charging IC supporting BC 1.2 SCL0 SCL0 Charging battery SDA0 SDA0 P16 or PB5 USB0_VBUS *1, *3...
Page 917 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.5 shows an example of host connection of the USB connector. External connection USB0_VBUSEN Power supply IC for non- OTG USB USB0_OVRCURA host VBUS At least 120 µF A connector transceiver VBUS USB0_DP USB0_DM...
Page 918 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.6 and Figure 32.7 show an example of functional connection of the USB connector in bus powered state. External connection Each system power B connector supply (3.3 V) System power Regulator VBUS supply (3.3 V) P16 or PB5...
Page 919 RX23W Group 32. USB 2.0 Host/Function Module (USBc) External connection B connector P16 or PB5 USB0_VBUS VBUS transceiver USB0_DP USB0_DM D– : Output impedance : Pull-up resistor Note 1. Design the board so that the total VBUS capacitance ranges from 1.0 to 10 µF. Figure 32.7 Functional Connection Sample of USB Connector in Bus Powered State (2) The examples of external circuits given in this section are simplified circuits, and their operation in every system is not...
Page 920: Interrupt Sources
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.2 Interrupt Sources Table 32.12 lists the interrupt sources in the USB. When an interrupt generation condition is satisfied and the interrupt output is enabled using the corresponding interrupt enable register, a USB interrupt request is issued the Interrupt Controller (ICU) and an USB interrupt will be generated. Table 32.12 Interrupt Sources Function...
Page 921 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.8 shows the circuits related to the interrupts in the USB. USBR USB bus reset detected INTENB0 INTSTS0 VBSE Set_Address detected VBINT Set_Configuration RSME USBI detected RESM SOFE Suspended state detected SOFR Control Write Data Stage DVSE...
Page 922: Interrupt Descriptions
RX23W Group 32. USB 2.0 Host/Function Module (USBc) Table 32.13 shows the interrupts generated in the USB0. Table 32.13 USB Interrupts Interrupt DMAC Name Interrupt Status Flag Activation Activation D0FIFO DMA/DTC transfer request 0 Possible Possible D1FIFO DMA/DTC transfer request 1 Possible Possible USBI...
Page 923 RX23W Group 32. USB 2.0 Host/Function Module (USBc) (b) For the pipe in the receiving direction:  When packet reception is completed successfully thus enabling the FIFO buffer to be read while read-access from the CPU to the FIFO buffer for the pertinent pipe is disabled (when the BSTS flag is read as 0). No request trigger is generated for the transaction in which data PID mismatch has occurred.
Page 924 RX23W Group 32. USB 2.0 Host/Function Module (USBc) (3) When the SOFCFG.BRDYM Bit = 1 and the PIPECFG.BFRE Bit = 0 With these settings, the BRDYSTS.PIPEnBRDY values are linked to the BSTS flag setting for each pipe. In other words, the BRDY interrupt status flags (PIPEnBRDY) are set to 1 or 0 by the USB depending on the FIFO buffer status.
Page 925 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.9 shows the timing of BRDY interrupt generation. (1) Example of zero-length packet reception or data packet reception when BFRE = 0 (single-buffer mode) Token Packet Data Packet ACK Handshake USB bus FIFO buffer status Ready for reception Ready for read access...
Page 926: Nrdy Interrupt
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.3.2 NRDY Interrupt On generating an internal NRDY interrupt request for the pipe whose PID[1:0] bits are set to 01b (BUF) by software, the USB sets the corresponding NRDYSTS.PIPEnNRDY flag to 1. If the corresponding bit in the NRDYENB register has been set to 1 by software, the USB sets the INTSTS0.NRDY flag to 1 and generates a USB interrupt.
Page 927 RX23W Group 32. USB 2.0 Host/Function Module (USBc)  For the pipe for isochronous transfers, when a CRC error or a bit stuffing error is detected in the received data packet. In this case, the USB sets the PIPEnNRDY flag corresponding to the pipe and the CRCE flag to 1. ...
Page 928 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.10 shows the timing of NRDY interrupt generation when the function controller is selected. (1) Example of data transmission (single-buffer mode) IN Token Packet USB bus NAK Handshake FIFO buffer status Ready for write access (there is no data to be transmitted) NRDY interrupt (NRDYSTS.PIPEnNRDY flag)
Page 929: Bemp Interrupt
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.3.3 BEMP Interrupt On detecting a BEMP interrupt for the pipe whose PID[1:0] bits are set to 01b (BUF) by software, the USB sets the corresponding BEMPSTS.PIPEnBEMP flag to 1. If the corresponding bit in the BEMPENB register has been set to 1 by software, the USB sets the INTSTS0.BEMP flag to 1 and generates a USB interrupt.
Page 930: Device State Transition Interrupt
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.3.4 Device State Transition Interrupt Figure 32.12 is a diagram of device state transitions in the USB. The USB controls device state and generates device state transition interrupts. However, recovery from the suspended state (resume signal detection) is detected by means of the resume interrupt.
Page 931: Control Transfer Stage Transition Interrupt
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.3.5 Control Transfer Stage Transition Interrupt Figure 32.13 is a diagram of control transfer stage transitions in the USB. The USB controls the control transfer sequence and generates control transfer stage transition interrupts. The control transfer stage transition interrupts can be enabled or disabled individually using INTENB0.
Page 932: Frame Update Interrupt
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.3.6 Frame Update Interrupt With the host controller selected, an interrupt is generated at the timing when the frame number is updated. With the function controller selected, an SOFR interrupt is generated when the frame number is updated. When the function controller is selected, the USB updates the frame number and generates an SOFR interrupt if it detects a new SOF packet during full-speed operation.
Page 933: Sack Interrupt
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.3.12 SACK Interrupt A SACK interrupt is generated when an ACK response for the transmitted setup packet has been received from the peripheral device with the host controller selected. The SACK interrupt can be used to confirm that the setup transaction has been completed successfully.
Page 934: Pipe Control
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.4 Pipe Control Table 32.15 lists the pipe settings for the USB. With USB data transfer, data transfer is carried out using the pipe that the software has associated with the endpoint. The USB has ten pipes that are used for data transfer. Appropriate settings should be made for each of the pipes according to the specifications of the system.
Page 935: Pipe Control Register Switching Procedures
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.4.1 Pipe Control Register Switching Procedures The following bits in the pipe control registers can be modified only when USB communication is prohibited (PID[1:0] = 00b (NAK)). The following shows the registers and bits that should not be modified when USB communication is enabled (PID[1:0] = 01b (BUF)).
Page 936: Maximum Packet Size Setting
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.4.4 Maximum Packet Size Setting The DCPMAXP.MXPS[6:0] bits and the PIPEMAXP.MXPS[8:0] bits are used to specify the maximum packet size for each pipe. DCP and PIPE1 to PIPE5 can be set to any of the maximum pipe sizes defined by USB Specification 2.0. For PIPE6 to PIPE9, 64 bytes are the upper limit of the maximum packet size.
Page 937: Response Pid
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.4.6 Response PID The PID[1:0] bits in the DCPCTR and PIPEnCTR registers are used to set the response PID for each pipe. The following shows the USB operation with various response PID settings: (1) Response PID settings when the host controller is selected: The response PID is used to specify the execution of transactions.
Page 938: Data Pid Sequence Bit
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.4.7 Data PID Sequence Bit The USB automatically toggles the sequence bit in the data PID when data is transferred successfully in the control transfer data stage, bulk transfer, and interrupt transfer. The sequence bit of the next data PID to be transmitted can be confirmed with the SQMON flag in the DCPCTR and PIPEnCTR registers.
Page 939: Null Auto Response Mode
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.4.11 Null Auto Response Mode With the pipes for bulk IN transfer, zero-length packets are continuously transmitted when the PIPEnCTR.ATREPM bit is set to 1. To make a transition from normal mode to null auto response mode, null auto response mode should be set in the pipe operation disabled state (response PID = NAK) before enabling pipe operation (response PID = BUF).
Page 940: Fifo Buffer Clearing
RX23W Group 32. USB 2.0 Host/Function Module (USBc) Table 32.17 Buffer Status Indicated by the INBUFM Flag INBUFM Buffer Memory Status 0 (receiving direction) Invalid Invalid 1 (transmitting direction) The transmission has been completed. There is no waiting data to be transmitted. 1 (transmitting direction) The FIFO port has written data to the buffer.
Page 941: Fifo Port Functions
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.5.3 FIFO Port Functions Table 32.19 shows the settings for the FIFO port functions of the USB. In write access, writing data until the maximum packet size is reached automatically enables transmission of the data. To enable transmission before the maximum packet size is reached, the BVAL bit in the port control register should be set to end writing.
Page 942: Dma Transfers (D0Fifo And D1Fifo Ports)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.5.4 DMA Transfers (D0FIFO and D1FIFO Ports) (1) Overview of DMA Transfers For PIPE1 to PIPE9, the FIFO port can be accessed using the DMAC. When accessing the buffer for the pipe targeted for DMA transfer is enabled, a DMA transfer request is issued.
Page 943: Control Transfers Using Dcp
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.6 Control Transfers Using DCP In the data stage of control transfers, data is transferred using the default control pipe (DCP). The DCP buffer memory is a 64-byte single buffer and is a fixed area that is shared for both control reading and control writing.
Page 944: Control Transfers When The Function Controller Is Selected
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.6.2 Control Transfers When the Function Controller is Selected (1) Setup Stage The USB sends an ACK response for a correct setup packet targeted to the USB. The operation of the USB in the setup stage is described below.
Page 945: Bulk Transfers (Pipe1 To Pipe5)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.7 Bulk Transfers (PIPE1 to PIPE5) The buffer memory usage (single/double buffer setting) can be selected for bulk transfers. The USB provides the following functions for bulk transfers.  BRDY interrupt function (PIPECFG.BFRE bit: refer to section 32.3.3.1 , (2) When the SOFCFG.BRDYM Bit = 0 and the PIPECFG.BFRE Bit = 1 ...
Page 946: Isochronous Transfers (Pipe1 And Pipe2)
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.9 Isochronous Transfers (PIPE1 and PIPE2) The USB has the following functions for isochronous transfers.  Notification of isochronous transfer error information  Interval counter (specified by the PIPEPERI.IITV[2:0] bits)  Isochronous IN transfer data setup control (IDLY function) ...
Page 947: Data Pid
RX23W Group 32. USB 2.0 Host/Function Module (USBc) Table 32.23 Error Detection When a Data Packet is Received Detection Priority Error Generated Interrupt and Status PID errors No interrupts are generated (ignored as a corrupted packet). CRC errors and bit stuffing An NRDY interrupt is generated to set the FRMNUM.CRCE to 1 bit in both cases when errors the host controller is selected and the function controller is selected.
Page 948 RX23W Group 32. USB 2.0 Host/Function Module (USBc) (1) Counter Initialization When the Function Controller is Selected The interval counter is initialized when the MCU is reset or when the PIPEnCTR.ACLRM bit is set to 1. Note that the PIPEPERI.IITV[2:0] bits are not initialized when the ACLRM bit is used for initialization. After the interval counter has been initialized, counting is started under either of the following conditions 1 and 2 when a packet has been transferred successfully.
Page 949 RX23W Group 32. USB 2.0 Host/Function Module (USBc) When the selected pipe is set for isochronous transfers, the USB carries out the following operation in addition to controlling the token issuance interval. The USB issues a token even when the NRDY interrupt generation condition is satisfied.
Page 950 RX23W Group 32. USB 2.0 Host/Function Module (USBc)  When the IITV[2:0] ≠ 000b: The interval counting starts on completion of successful reception of the first data packet after the PID[1:0] bits for the selected pipe have been modified to 01b (BUF). USB bus PID bit setting Token...
Page 951 RX23W Group 32. USB 2.0 Host/Function Module (USBc) (4) Setup of Data to be Transmitted Using Isochronous Transfer When the Function Controller is Selected With isochronous data transmission using the USB in the function controller, after data has been written to the buffer memory, a data packet can be transmitted with the next frame after the frame in which an SOF packet is detected.
Page 952 RX23W Group 32. USB 2.0 Host/Function Module (USBc) (5) Isochronous Transfer Transmission Buffer Flush When the Function Controller is Selected If an SOF packet of the next frame is received without receiving an IN token in an interval frame during isochronous data transmission, the USB operates as if an IN token had been corrupted, and clears the buffer for which transmission is enabled, putting that buffer in the writing enabled state.
Page 953 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Figure 32.20 shows an example of interval error occurrence in the USB. There are five types of interval errors, as shown below. The interval error is generated at the timing indicated by in the figure, and the buffer flush function is activated.
Page 954: Sof Interpolation Function
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.10 SOF Interpolation Function When the function controller is selected and if data could not be received at intervals of 1 ms because an SOF packet was corrupted or missing, the USB interpolates the SOF. The SOF interpolation operation begins when the USBE and SCKE bits in the SYSCFG register have been set to 1 and an SOF packet is received.
Page 955: Pipe Schedule
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.3.11 Pipe Schedule 32.3.11.1 Conditions for Generating a Transaction When the host controller is selected and the DVSTCTR0.UACT bit has been set to 1, the USB generates a transaction under the conditions shown in Table 32.25 . Table 32.25 Conditions for Generating a Transaction Conditions for Generation...
Page 956: Usage Notes
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.4 Usage Notes 32.4.1 Setting the Module Stop Function Operation of the USB module can be disabled or enabled using module stop control register B (MSTPCRB). The setting after a reset is for operation of the USB module to be stopped. Register access is enabled by releasing the module stop state.
Page 957: Battery Charging Detection Processing
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.5 Battery Charging Detection Processing It is possible to control the processing for data contact detection (D+ line contact check), primary detection (charger detection), and secondary detection (charger verification), which are defined in the battery charging specification. The following describes required operations for a function device and a host device, individually.
Page 958 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Detect VBUS Set BATCHGE0 bit to 1 Set CNEN bit to 1 Data Contact Detection Data Contact Set RPDME0 bit to 1 (software waiting method) Detection Set IDPSRCE0 bit to 1 (hardware Wait for min.
Page 959: Processing When Host Controller Is Selected
RX23W Group 32. USB 2.0 Host/Function Module (USBc) 32.5.2 Processing When Host Controller is Selected The following processing is required when operating the USB module as a charging downstream port for battery charging. (1) Start driving the VBUS. (2) Enable the portable device detection circuit. (3) Monitor the portable device detection signal, and start driving the D–...
Page 960 RX23W Group 32. USB 2.0 Host/Function Module (USBc) Portable Device Detection Drive VBUS Processing PD detection circuit enabled (IDPSINKE0 = 1) PD detection interrupt enabled (PDDETINTE0 = 1) PD detection interrupt? (PDDETINT) Connection detected? Repeat reading several times (D+ pull-up detected?) to perform debouncing.
Page 961 RX23W Group 32. USB 2.0 Host/Function Module (USBc) D-Line Drive Control Drive VBUS Set VDMSRCE0 bit to 1 Connection detected? Set VDMSRCE0 bit to 0 (within 10 ms) Normal state Disconnection detected? Set VDMSRCE0 bit to 1 (within 200 ms) Figure 32.23 Process Flow for Operating as Charging Downstream Port (Steps (A) to (B)) R01UH0823EJ0100 Rev.1.00...
Page 962: Serial Communications Interface (Scig, Scih)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Serial Communications Interface (SCIg, SCIh) This MCU has four independent serial communications interface (SCI) channels. The SCI consists of the SCIg module (SCI1, SCI5, and SCI8) and the SCIh module (SCI12). The SCIg module (SCI1, SCI5, and SCI8) can handle both asynchronous and clock synchronous serial communications. Asynchronous serial data communications can be carried out with standard asynchronous communications chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA).
Page 963 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.1 SCIg Specifications (2/2) Item Description Clock synchronous Data length 8 bits mode Receive error detection Overrun error Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception. Smart card interface Error processing An error signal can be automatically transmitted when detecting a parity error during...
Page 964 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.2 SCIh Specifications (2/2) Item Description Asynchronous Data length 7, 8, or 9 bits mode Transmission stop bit 1 or 2 bits Parity Even parity, odd parity, or no parity Receive error detection Parity, overrun, and framing errors Hardware flow control CTSn# and RTSn# pins can be used in controlling transmission/reception.
Page 965 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.3 Functions of SCI Channels Item SCI1, SCI8 SCI5 SCI12 Asynchronous mode Available Available Available Clock synchronous mode Available Available Available Smart card interface mode Available Available Available Simple I C mode Available Available Available...
Page 966 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Module data bus RDRH TDRH PCLK RDR(L) TDR(L) MDDR PCLK/4 Baud rate Clock PCLK/16 SCMR generator PCLK/64 SEMR SNFR RXDn/ SIMR1 SSCLn/ SIMR2 SMISOn SIMR3 TXDn/ SISR TMO0 SSDAn/ SPMR TMO1 SMOSIn RTSn#/ CTSn#/ TEI interrupt request...
Page 967 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) SCK12 RTS12#/CTS12#/SS12# TMO0 TMO1 Extended serial mode control section RXD12/SSCL12/ SMISO12/RXDX12 TXD12/SSDA12/ SMOSI12/TXDX12/ SIOX12 Transmit/ Controller receive SCIX0 interrupt request block SCIX1 interrupt request SCIX2 interrupt request SCIX3 interrupt request Timer RXI interrupt request TXI interrupt request TEI interrupt request ERI interrupt request...
Page 968 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.4 to Table 33.7 list the pin configuration of the SCIs for the individual modes. Table 33.4 SCI Pin Configuration in Asynchronous Mode and Clock Synchronous Mode Channel Pin Name Function SCI1 SCK1 SCI1 clock input/output...
Page 969 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.6 SCI Pin Configuration in Simple SPI Mode (2/2) Channel Pin Name Function SCI12 SCK12 SCI12 clock input/output SMISO12 SCI12 slave transmit data input/output SMOSI12 SCI12 master transmit data input/output SS12# Input SCI12 chip select input Table 33.7...
Page 970: Register Descriptions
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2 Register Descriptions 33.2.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RXDn pin and converts it into parallel data. When one frame of data has been received, it is automatically transferred to the RDR register. The RSR register cannot be directly accessed by the CPU.
Page 971: Receive Data Register H, L, Hl (Rdrh, Rdrl, Rdrhl)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.3 Receive Data Register H, L, HL (RDRH, RDRL, RDRHL)  Receive Data Register H (RDRH) Address(es): SCI1.RDRH 0008 A030h, SCI5.RDRH 0008 A0B0h, SCI8.RDRH 0008 A110h, SCI12.RDRH 0008 B310h  Receive Data Register L (RDRL) Address(es): SCI1.RDRL 0008 A031h, SCI5.RDRL 0008 A0B1h, SCI8.RDRL 0008 A111h, SCI12.RDRL 0008 B311h ...
Page 972: Transmit Data Register H, L, Hl (Tdrh, Tdrl, Tdrhl)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.5 Transmit Data Register H, L, HL (TDRH, TDRL, TDRHL)  Transmit Data Register H (TDRH) Address(es): SCI1.TDRH 0008 A02Eh, SCI5.TDRH 0008 A0AEh, SCI8.TDRH 0008 A10Eh, SCI12.TDRH 0008 B30Eh  Transmit Data Register L (TDRL) Address(es): SCI1.TDRL 0008 A02Fh, SCI5.TDRL 0008 A0AFh, SCI8.TDRL 0008 A10Fh, SCI12.TDRL 0008 B30Fh ...
Page 973: Serial Mode Register (Smr)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.7 Serial Mode Register (SMR) Note: Some bits in SMR have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SMR 0008 A020h, SCI5.SMR 0008 A0A0h, SCI8.SMR 0008 A100h, SCI12.SMR 0008 B300h STOP CKS[1:0] Value after reset:...
Page 974 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) STOP Bit (Stop Bit Length) Selects the stop bit length in transmission. In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
Page 975 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SMR 0008 A020h, SMCI5.SMR 0008 A0A0h, SMCI8.SMR 0008 A100h, SMCI12.SMR 0008 B300h BCP[1:0] CKS[1:0] Value after reset: Symbol Bit Name Description b1, b0 CKS[1:0] Clock Select b1 b0...
Page 976 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) PM Bit (Parity Mode) Selects the parity mode for transmission and reception (even or odd). For details on the usage of this bit in smart card interface mode, refer to section 33.6.2, Data Format (Except in Block Transfer Mode) .
Page 977: Serial Control Register (Scr)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.8 Serial Control Register (SCR) Note: Some bits in the SCR register have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SCR 0008 A022h, SCI5.SCR 0008 A0A2h, SCI8.SCR 0008 A102h, SCI12.SCR 0008 B302h MPIE TEIE...
Page 978 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) CKE[1:0] Bits (Clock Enable) These bits select the clock source and SCKn pin function. The combination of the settings of these bits and of the SEMR.ACS0 bit sets the internal TMR clock. TEIE Bit (Transmit End Interrupt Enable) Enables or disables a TEI interrupt request.
Page 979 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SCR 0008 A022h, SMCI5.SCR 0008 A0A2h, SMCI8.SCR 0008 A102h, SMCI12.SCR 0008 B302h MPIE TEIE CKE[1:0] Value after reset: Symbol Bit Name Description  When SMR.GM = 0 b1, b0 CKE[1:0] Clock Enable...
Page 980 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) RE Bit (Receive Enable) Enables or disables serial reception. When this bit is set to 1, serial reception is started by detecting the start bit. Note that the SMR register should be set prior to setting the RE bit to 1 in order to designate the reception format.
Page 981: Serial Status Register (Ssr)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.9 Serial Status Register (SSR) Some bits in the SSR register have different functions in smart card interface mode and non-smart card interface mode. (1) Non-Smart Card Interface Mode (SCMR.SMIF = 0) Address(es): SCI1.SSR 0008 A024h, SCI5.SSR 0008 A0A4h, SCI8.SSR 0008 A104h, SCI12.SSR 0008 B304h TDRE RDRF ORER...
Page 982 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]  When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 983 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) TDRE Flag (Transmit Data Empty Flag) Indicates whether the TDR register has data to be transmitted. [Setting condition]  When data is transferred from TDR to TSR [Clearing condition]  When data is written to TDR R01UH0823EJ0100 Rev.1.00 Page 983 of 1823 Jul 31, 2019...
Page 984 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) (2) Smart Card Interface Mode (SCMR.SMIF = 1) Address(es): SMCI1.SSR 0008 A024h, SMCI5.SSR 0008 A0A4h, SMCI8.SSR 0008 A104h, SMCI12.SSR 0008 B304h TDRE RDRF ORER TEND MPBT Value after reset: Symbol Bit Name Description MPBT Multi-Processor Bit Transfer...
Page 985 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition]  When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 986: Smart Card Mode Register (Scmr)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.10 Smart Card Mode Register (SCMR) Address(es): SCI1.SCMR 0008 A026h, SCI5.SCMR 0008 A0A6h, SCI8.SCMR 0008 A106h, SCI12.SCMR 0008 B306h, SMCI1.SCMR 0008 A026h, SMCI5.SCMR 0008 A0A6h, SMCI8.SCMR 0008 A106h, SMCI12.SCMR 0008 B306h BCP2 —...
Page 987 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) BCP2 Bit (Base Clock Pulse 2) Selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this bit in combination with the SMR.BCP[1:0] bits. Table 33.9 Combinations of the SCMR.BCP2 Bit and SMR.BCP[1:0] Bits SCMR.BCP2 Bit...
Page 988: Bit Rate Register (Brr)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.11 Bit Rate Register (BRR) Address(es): SCI1.BRR 0008 A021h, SCI5.BRR 0008 A0A1h, SCI8.BRR 0008 A101h, SCI12.BRR 0008 B301h Value after reset: The BRR register is an 8-bit register that adjusts the bit rate. As each SCI channel has independent baud rate generator control, different bit rates can be set for each.
Page 989 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.12 Clock Source Settings SMR.CKS[1:0] Bit Setting Clock Source PCLK PCLK/4 PCLK/16 PCLK/64 Table 33.13 Base Clock Settings in Smart Card Interface Mode SCMR.BCP2 Bit Setting SMR.BCP[1:0] Bit Setting Base Clock Cycles for 1-bit Period 93 clock cycles 128 clock cycles 186 clock cycles...
Page 990 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.14 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency PCLK (MHz) 9.8304 12.288 Bit Rate (bps) Error (%) n Error (%) n Error (%) n Error (%) n Error (%) 0.03 –0.26...
Page 991 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.15 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) SEMR Settings SEMR Settings PCLK BGDM ABCS Maximum Bit Rate PCLK BGDM ABCS Maximum Bit Rate (MHz) (bps) (MHz) (bps) 250000 17.2032 537600 500000...
Page 992 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.16 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Maximum Bit Rate (bps) PCLK (MHz) External Input Clock (MHz) SEMR.ABCS Bit = 0 SEMR.ABCS Bit = 1 2.0000 125000 250000 9.8304 2.4576 153600...
Page 993 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.18 BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) 2.5 k 10 k 25 k 50 k 100 k 250 k 500 k —...
Page 994 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.20 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Bit Rate (bps) PCLK (MHz) Error (%) 9600 7.1424 0.00 10.00 –30.00 10.7136 –25.00 13.00 –8.99 14.2848...
Page 995 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Table 33.22 BRR Settings for Various Bit Rates (Simple I C Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) Error (%) n Error (%) n Error (%) n Error (%) n Error (%) 10 k –2.3 –3.8...
Page 996: Modulation Duty Register (Mddr)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.12 Modulation Duty Register (MDDR) Address(es): SCI1.MDDR 0008 A032h, SCI5.MDDR 0008 A0B2h, SCI8.MDDR 0008 A112h, SCI12.MDDR 0008 B312h Value after reset: The MDDR register corrects the bit rate adjusted by the BRR register. When the SEMR.BRME bit is set to 1, the bit rate generated by the on-chip baud rate generator is evenly corrected according to the settings of the MDDR register (M/256).
Page 997: Serial Extended Mode Register (Semr)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Smaller settings of the SMR.CKS[1:0] bits and larger settings of the BRR register reduce difference in the length of the 1-bit period. 33.2.13 Serial Extended Mode Register (SEMR) Address(es): SCI1.SEMR 0008 A027h, SCI5.SEMR 0008 A0A7h, SCI8.SEMR 0008 A107h, SCI12.SEMR 0008 B307h RXDES BGDM NFEN ABCS...
Page 998 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) ACS0 Bit (Asynchronous Mode Clock Source Select) Selects the clock source in the asynchronous mode. The ACS0 bit is valid in asynchronous mode (SMR.CM bit = 0) and when an external clock input is selected (SCR.CKE[1:0] bits = 10b or 11b).
Page 999 RX23W Group 33. Serial Communications Interface (SCIg, SCIh) BRME Bit (Bit Rate Modulation Enable) Enables and disables the bit rate modulation function. The bit rate generated by on-chip baud rate generator is evenly corrected when this function is enabled. NFEN Bit (Digital Noise Filter Function Enable) This bit enables or disables the digital noise filter function.
Page 1000: Noise Filter Setting Register (Snfr)
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.2.14 Noise Filter Setting Register (SNFR) Address(es): SCI1.SNFR 0008 A028h, SCI5.SNFR 0008 A0A8h, SCI8.SNFR 0008 A108h, SCI12.SNFR 0008 B308h — — — — — NFCS[2:0] Value after reset: Symbol Bit Name Description b2 to b0 NFCS[2:0] Noise Filter Clock Select...

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