Flash Reset Register (Fresetr); Flash Area Select Register (Fasr) - Renesas RX100 Series User Manual

RX13T Group
31.4.7

Flash Reset Register (FRESETR)

Address(es): FLASH.FRESETR 007F FF89h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 FRESET Flash Reset
b7 to b1 — Reserved
FRESET Bit (Flash Reset)
When this bit is set to 1, registers FASR, FSARH, FSARL, FEARH, FEARL, FWBH, FWBL, FCR, and FEXCR are
reset. Also, the values of registers FEAMH and FEAML are undefined. Do not access these registers during a reset. To
release the reset, set this bit to 0.
Do not write to this register while executing a software command or rewriting the extra area.
31.4.8

Flash Area Select Register (FASR)

Address(es): FLASH.FASR 007F FF81h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 EXS Extra Area Select
b7 to b1 — Reserved
Data can be written to the FASR register in ROM P/E mode or E2 DataFlash P/E mode.
This register is initialized by a reset or setting the FRESETR.FRESET bit to 1.
Data cannot be written to this register while the FRESETR.FRESET bit is 1.
EXS Bit (Extra Area Select)
Set this bit to 1 before issuing a software command (unique ID read, start-up area information program, or access
window information program) for the extra area. Set this bit to 0 before issuing a software command (program, blank
check, or block erase) for the user area.
After issuing a software command, do not change the value until changing it for issuing the next software command.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
b5 b4 b3 b2
— — — —
0 0 0 0
b1 b0
FRESE
—
T
0 0
Description
0: Flash control circuit reset is released.
1: Flash control circuit is reset.
These bits are read as 0. The write value should be 0.
b1 b0
— EXS
0 0
Description
0: User area or data area
1: Extra area
These bits are read as 0. The write value should be 0.
31. Flash Memory (FLASH)
R/W
R/W
R/W
R/W
R/W
R/W
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