I 2 C-Bus Mode Register 1 (Icmr1) - Renesas RX100 Series User Manual

RX13T Group
2
24.2.3 I C-bus Mode Register 1 (ICMR1)
Address(es): RIIC0.ICMR1 0008 8302h
b7 b6
MTWP
0 0
Value after reset:
Bit Symbol Bit Name
b2 to b0 BC[2:0] Bit Counter
b3 BCWP BC Write Protect
b6 to b4 CKS[2:0] Internal Reference Clock Select
b7 MTWP MST/TRS Write Protect
Note 1. Rewrite the BC[2:0] bits and set the BCWP bit to 0 at the same time.
BC[2:0] Bits (Bit Counter)
These bits function as a counter that indicates the number of bits remaining to be transferred at the detection of a rising
edge on the SCL0 line. Although these bits are writable and readable, it is not necessary to access these bits under normal
conditions.
To write to these bits, specify the number of bits to be transferred plus one (data is transferred with an additional
acknowledge bit) between transferred bytes when the SCL0 line is at a low level.
The values of the BC[2:0] bits return to 000b at the end of a data transfer including the acknowledge bit or when a start
condition including a restart condition is detected.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
CKS[2:0] BCWP
0 0 1 0
b1 b0
BC[2:0]
0 0
Description
b2 b0
0 0 0: 9 bits
0 0 1: 2 bits
0 1 0: 3 bits
0 1 1: 4 bits
1 0 0: 5 bits
1 0 1: 6 bits
1 1 0: 7 bits
1 1 1: 8 bits
0: Enables a value to be written in the BC[2:0] bits.
(This bit is read as 1.)
Select the internal reference clock (IICφ) source for the RIIC.
b6 b4
0 0 0: PCLK/1 clock
0 0 1: PCLK/2 clock
0 1 0: PCLK/4 clock
0 1 1: PCLK/8 clock
1 0 0: PCLK/16 clock
1 0 1: PCLK/32 clock
1 1 0: PCLK/64 clock
1 1 1: PCLK/128 clock
0: Disables writing to the ICCR2.MST and TRS bits.
1: Enables writing to the ICCR2.MST and TRS bits.
2
24. I C-bus Interface (RIICa)
R/W
R/W*
R/W*
R/W
R/W
Page 733 of 1041
1
1