Renesas RX100 Series User Manual page 68

RX13T Group
Table 2.14 Instructions that are Converted into Multiple Micro-Operations (2/2)
Instruction
String manipulation instructions*
Floating-point operation
instructions (register-register,
immediate-register)
Floating-point operation
instructions (memory source
operand)
System manipulation instructions  RTE
?: Conditional operator
Note 1. floor(x): Max. integer that is smaller than x
Note 2. For the number of cycles for throughput and latency, refer to section 2.8.3, Calculation of the Instruction Processing Time.
Note 3. The PUSHM instruction is converted into multiple store operations. The pipeline processing is the same as the one for the store
operations of the MOV instruction, where the operation is repeated for the number of specified registers.
Note 4. The POPM instruction is converted into multiple load operations. The pipeline processing is the same as the one for the load
operations of the MOV instruction, where the operation is repeated for the number of specified registers.
Note 5. Each of the SCMPU, SMOVU, SWHILE, and SUNTIL instructions ends the execution regardless of the specified cycles, if the
end condition is satisfied during execution.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Mnemonic (indicates the common operation when
the size is omitted)
5  SCMPU
 SMOVB
 SMOVF, SMOVU
 SSTR.B
 SSTR.W
 SSTR.L
 SUNTIL.B, SWHILE.B
 SUNTIL.W, SWHILE.W
 SUNTIL.L, SWHILE.L
 {FADD, FSUB} "#IMM, Rd"/"Rs, Rd"
 FMUL "#IMM, Rd"/"Rs, Rd"
 FDIV "#IMM, Rd"/"Rs, Rd"
 {FTOI, ROUND, ITOF} "Rs, Rd"
 {FADD, FSUB} "[Rs], Rd"/"dsp[Rs], Rd"
 FCMP "[Rs], Rs2"/"dsp[Rs], Rs2"
 FMUL "[Rs], Rd"/"dsp[Rs], Rd"
 FDIV "[Rs], Rd"/"dsp[Rs], Rd"
 {FTOI, ROUND, ITOF} "[Rs], Rd"/
"dsp[Rs], Rd"
 RTFI
Reference
Figure Number of Cycles
— 2+4×floor(n/4)+4×(n%4)
n: Number of comparison
1
bytes*
— n>3?
6+3×floor(n/4)+3×(n%4):
2+3n
n: Number of transfer
1
bytes*
— 2+3×floor(n/4)+3×(n%4)
n: Number of transfer
1
bytes*
— 2+floor(n/4)+n%4
n: Number of transfer
1
bytes*
— 2+floor(n/2)+n%2
n: Number of transfer
1
words*
— 2+n
n: Number of transfer
longwords
— 3+3×floor(n/4)+3×(n%4)
n: Number of comparison
1
bytes*
— 3+3×floor(n/2)+3×(n%2)
n: Number of comparison
1
words*
— 3+3×n
n: Number of comparison
longwords
Figure 2.15 4
— 3
— 16
— 2
— 6
— 3
— 5
— 18
— 4
— 6
— 3
Page 68 of 1041
2. CPU