Operation In Master Transmission (Simple I 2 C Mode) - Renesas RX100 Series User Manual

RX13T Group
23.7.5 Operation in Master Transmission (Simple I
Figure 23.51 and Figure 23.52 show examples of operations in master transmission and Figure 23.53 is a flowchart
showing the procedure for data transmission. Refer to Table 23.33 for more information on the STI interrupt.
When 10-bit slave addresses are in use, steps [3] and [4] in Figure 23.53 are repeated twice.
2
In simple I C mode, the transmit data empty interrupt (TXI) is generated when communication of one frame is
completed, unlike the TXI interrupt request generation timing during clock synchronous transmission.
Start condition
SSCLn
SSDAn
TXI interrupt flag
1
(IRn in the ICU* )
STI interrupt flag
1
(IRn in the ICU* )
Generation of STI interrupt
SISR.IICACKR flag
Note1. Refer to section 14, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.
Figure 23.51 Example 1 of Operations for Master Transmission in Simple I
(with 7-Bit Slave Addresses, Transmission Interrupts, and Reception Interrupts in Use)
When the SIMR2.IICINTM bit is set to 0 (use ACK/NACK interrupts) during master transmission, the DTC is activated
by the ACK interrupt as the trigger and necessary number of data bytes are transmitted. When the NACK is received,
error processing, such as transmission stop and retransmission, is performed by the NACK interrupt as the trigger.
Start condition
SSCLn
SSDAn
TXI interrupt flag
1
(IRn in the ICU* )
RXI interrupt flag
1
(IRn in the ICU* )
STI interrupt flag
1
(IRn in the ICU* )
Generation of STI interrupt request
Note1. Refer to section 14, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.
Figure 23.52 Example 2 of Operations for Master Transmission in Simple I
(with 7-Bit Slave Addresses, ACK Interrupts, and NACK Interrupts in Use)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Slave address (7 bits)
W#
ACK
D7 D6 D1 D0
Generation of TXI interrupt request
Acceptance of request
Slave address (7 bits)
W#
D7 D6 D1 D0 ACK
Generation of RXI interrupt request
Acceptance of STI interrupt request
23. Serial Communications Interface (SCIg, SCIh)
2
C Mode)
Transmitted data
D7 D6 D1
Acceptance of TXI interrupt request
Generation of TXI interrupt request
Reception of NACK
Reception of ACK
2
C-bus Mode
Transmitted data
D7 D6 D1
Generation of TXI interrupt request
Acceptance or RXI interrupt request
2
C-bus Mode
Stop condition
D0 ACK/NACK
Generation of request
Reception of ACK
Stop condition
D0 NACK
Acceptance of TXI
interrupt request
Generation of STI interrupt request
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