Control Register 0 (Cr0); Control Register 1 (Cr1) - Renesas RX100 Series User Manual

32-bit mcu
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23.2.21

Control Register 0 (CR0)

Address(es): SCI12.CR0 0008 B321h
b7
b6
Value after reset:
0
0
Bit
Symbol
Bit Name
b0
Reserved
b1
SFSF
Start Frame Status Flag
b2
RXDSF
RXDX12 Input Status Flag
b3
BRME
Bit Rate Measurement
Enable
b7 to b4
Reserved
23.2.22

Control Register 1 (CR1)

Address(es): SCI12.CR1 0008 B322h
b7
b6
PIBS[2:0]
0
0
Value after reset:
Bit
Symbol
b0
BFE
b1
CF0RE
b3, b2
CF1DS[1:0]
b4
PIBE
b7 to b5
PIBS[2:0]
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5
b4
b3
b2
BRME RXDSF SFSF
0
0
0
0
Description
This bit is read as 0. The write value should be 0.
0: Start Frame detection function is disabled.
1: Start Frame detection function is enabled.
0: RXDX12 input is enabled.
1: RXDX12 input is disabled.
0: Measurement of bit rate is disabled.
1: Measurement of bit rate is enabled.
These bits are read as 0. The write value should be 0.
b5
b4
b3
b2
PIBE
CF1DS[1:0]
0
0
0
0
Bit Name
Break Field Enable
Control Field 0 Reception
Enable
Control Field 1 Data Register
Select
Priority Interrupt Bit Enable
Priority Interrupt Bit Select
23. Serial Communications Interface (SCIg, SCIh)
b1
b0
0
0
b1
b0
CF0RE
BFE
0
0
Description
0: Break Field detection is disabled.
1: Break Field detection is enabled.
0: Reception of Control Field 0 is disabled.
1: Reception of Control Field 0 is enabled.
b3 b2
0 0: Selects comparison with the value in PCF1DR.
0 1: Selects comparison with the value in SCF1DR.
1 0: Selects comparison with the values in PCF1DR and
SCF1DR.
1 1: Setting prohibited.
0: The priority interrupt bit is disabled.
1: The priority interrupt bit is enabled.
b7
b5
0 0 0: 0th bit of Control Field 1
0 0 1: 1st bit of Control Field 1
0 1 0: 2nd bit of Control Field 1
0 1 1: 3rd bit of Control Field 1
1 0 0: 4th bit of Control Field 1
1 0 1: 5th bit of Control Field 1
1 1 0: 6th bit of Control Field 1
1 1 1: 7th bit of Control Field 1
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Page 626 of 1041

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