Operation; Comparator Operation Example - Renesas RX100 Series User Manual

RX13T Group
28.3

Operation

28.3.1

Comparator Operation Example

Figure 28.2 shows an operation example of the comparator. The COMPn level detection signal (n = 0 to 2) becomes
high when the analog input voltage is higher than the reference input voltage, and the COMPn level detection signal
becomes low when the analog input voltage is lower than the reference input voltage (when the CMPCTL.CINV bit is 0).
When the CPOE bit in the corresponding CMPIOC register is 1, the COMPn level detection signal is output from the
COMPn pin. Interrupt request is output in response to changes in the comparator output.
Reference
input voltage
(CVREFC0 or
D/A converter 0
output voltage)
COMPn level
1
detection signal
0
COMPn interrupt request
output
High
COMPn output
Low
n = 0 to 2
Note: The above diagram applies when the CMPIOC.CPOE bit is 1 (pin output enabled), the CMPCTL.CDFS[1:0] bits are
00b (filter not used), the CMPCTL.CEG[1:0] bits are 11b (both edges selected), and the CMPCTL.CINV bit is 0
(comparator output not inverted).
Figure 28.2 Comparator Operation Example
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
(A) (B)
After COMPn output, an interrupt request is generated
with a delay of 2 or 3 operating clocks.
28. Comparator C (CMPC)
(A) (B)
Page 895 of 1041