Register Descriptions; Option Function Select Register 0 (Ofs0) - Renesas RX100 Series User Manual

RX13T Group
7.2

Register Descriptions

7.2.1

Option Function Select Register 0 (OFS0)

Address(es): OFSM.OFS0 FFFF FF8Ch
b31 b30
— —
Value after reset:
b15 b14
IWDTS
—
LCSTP
Value after reset:
Bit Symbol
b0 —
b1 IWDTSTRT
b3, b2 IWDTTOPS[1:0]
b7 to b4 IWDTCKS[3:0]
b9, b8 IWDTRPES[1:0]
b11, b10 IWDTRPSS[1:0]
b12 IWDTRSTIRQS
b13 —
b14 IWDTSLCSTP
b31 to b15 —
Note 1. The value of the blank product is FFFF FFFFh. This register is set to a specified value after programming of the flash memory
with the user program.
The OFS0 register is allocated in the ROM. Set this register at the same time as writing the program. After writing to the
OFS0 register once, do not write to it again.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b29 b28 b27 b26
— — — —
b13 b12 b11 b10
IWDTR
— IWDTRPSS[1:0] IWDTRPES[1:0]
STIRQS
Bit Name
Reserved
IWDT Start Mode Select
IWDT Timeout Period Select
IWDT Clock Frequency
Division Ratio Select
IWDT Window End Position
Select
IWDT Window Start Position
Select
IWDT Reset Interrupt
Request Select
Reserved
IWDT Sleep Mode Count
Stop Control
Reserved
b25 b24 b23 b22
— — — —
The value set by the user* 1
b9 b8 b7 b6
IWDTCKS[3:0]
1
The value set by the user*
Description
When reading, this bit returns the value written by the user.
The write value should be 1.
0: IWDT is automatically activated in auto-start mode after a
reset
1: IWDT is halted after a reset
b3 b2
0 0: 128 cycles (007Fh)
0 1: 512 cycles (01FFh)
1 0: 1024 cycles (03FFh)
1 1: 2048 cycles (07FFh)
b7 b4
0 0 0 0: No division
0 0 1 0: Divide-by-16
0 0 1 1: Divide-by-32
0 1 0 0: Divide-by-64
1 1 1 1: Divide-by-128
0 1 0 1: Divide-by-256
Settings other than above are prohibited.
b9 b8
0 0: 75%
0 1: 50%
1 0: 25%
1 1: 0% (No window end position setting)
b11 b10
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100% (No window start position setting)
0: Non-maskable interrupt request is enabled
1: Reset is enabled
When reading, this bit returns the value written by the user.
The write value should be 1.
0: Counting stop is disabled
1: Counting stop is enabled when entering sleep, software
standby, or deep sleep mode
When reading, these bits return the value written by the
user. The write value should be 1.
7. Option-Setting Memory (OFSM)
b21 b20 b19 b18
— — — —
b5 b4 b3 b2
IWDTTOPS[1:0] IWDTS
Page 107 of 1041
b17 b16
— —
b1 b0
—
TRT
R/W
R
R
R
R
R
R
R
R
R
R