Compare Match Timer (Cmt); Overview - Renesas RX100 Series User Manual

RX13T Group
21.

Compare Match Timer (CMT)

This MCU has an on-chip compare match timer (CMT) unit (unit 0) consisting of a two-channel 16-bit timer (i.e., a total
of two channels). The CMT has a 16-bit counter, and can generate interrupts at set intervals.
In this section, "PCLK" is used to refer to PCLKB.
21.1

Overview

Table 21.1 lists the specifications for the CMT.
Figure 21.1 shows a block diagram of the CMT (unit 0). A two-channel CMT constitutes a unit.
Table 21.1 CMT Specifications
Item
Count clocks
Interrupt
Low power consumption function Module stop state can be set.
CMI0
Control circuit
CMSTR0: Compare match timer start register 0
CMCR: Compare match timer control register
CMCOR: Compare match timer constant register
CMCNT: Compare match timer counter
CMI: Compare match interrupt
Figure 21.1 CMT (Unit 0) Block Diagram
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
 Four frequency dividing clocks
One clock from PCLK/8, PCLK/32, PCLK/128, and PCLK/512 can be selected for each channel.
A compare match interrupt can be requested for each channel.
PCLK/32 PCLK/512
PCLK/8
PCLK/128
Clock selection
Module bus
21. Compare Match Timer (CMT)
PCLK/32
CMI1
PCLK/8
Control circuit Clock selection
Bus interface
PCLK/512
PCLK/128
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