Contention Between Buffer Register Write And Tcnt Clear Operations; Contention Between Tgr Read Operation And Input Capture - Renesas RX100 Series User Manual

RX13T Group
19.6.8

Contention between Buffer Register Write and TCNT Clear Operations

When the buffer transfer timing is set at the TCNT clear timing by the timer buffer transfer mode register (TBTM), if
TCNT clearing occurs in the TGR write cycle, the data before write operation is transferred to TGR by the buffer
operation.
Figure 19.127 shows the timing in this case.
TCNT clear signal
Buffer transfer signal
Buffer register
Figure 19.127 Contention between Buffer Register Write and TCNT Clear Operations
19.6.9

Contention between TGR Read Operation and Input Capture

If an input capture signal is generated in a TGR read cycle, the data before input capture transfer is read.
Figure 19.128 shows the timing in this case.
Input capture signal
Internal data bus
Figure 19.128 Contention between TGR Read Operation and Input Capture (MTU0 to MTU5)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
PCLKB
TGR
PCLKB
TGR
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Written by CPU
N M
N
Read by CPU
N M
N
Buffer register write data
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