Transfer Information Write-Back Skip Function; Write-Back Skip By Fixing Addresses; Write-Back Skip By The Mra.wbdis Bit - Renesas RX100 Series User Manual

RX13T Group
16.4.2

Transfer Information Write-Back Skip Function

16.4.2.1

Write-Back Skip by Fixing Addresses

When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to "address is fixed" (00b or 01b), a part of transfer
information is not written back. This function is performed independently of the setting of short-address mode or full-
address mode.
Table 16.5 lists transfer information write-back skip conditions and applicable registers. The CRA and CRB registers
are written back independently of the setting of short-address mode or full-address mode.
Furthermore, in full-address mode, write-back of registers MRA, MRB, and MRC is skipped.
Table 16.5 Transfer Information Write-Back Skip Conditions and Applicable Registers
MRA.SM[1:0] Bits
b3 b2
0 0
0 0
0 1
0 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
1 0
1 0
1 1
1 1
16.4.2.2

Write-Back Skip by the MRA.WBDIS Bit

When the MRA.WBDIS bit is 1, the transfer information (SAR, DAR, CRA, and CRB) is not written back regardless of
the settings of the transfer information.
The transfer information on the memory is not updated, data can be transferred by the DTC without copying the transfer
information from ROM to RAM. Skipping a write-back reduces time for post-processing of the data transfer.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
MRB.DM[1:0] Bits
b3 b2
0 0
0 1
0 0
0 1
1 0
1 1
1 0
1 1
0 0
0 1
0 0
0 1
1 0
1 1
1 0
1 1
16. Data Transfer Controller (DTCb)
SAR Register
Skip
Skip
Write-back
Write-back
DAR Register
Skip
Write-back
Skip
Write-back
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